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參數(shù)資料
| 型號(hào)： | LT8500IUHH#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWM GENERATOR 56-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | PWM 發(fā)生器 |
| PLL： | 無 |
| 主要目的： | LED 照明 |
| 輸入： | CMOS，TTL |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 0.075 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 50MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN-EP（5x9） |
| 包裝： | 帶卷 (TR) |
LT8500
8
8500f
operaTion
OVERVIEW
The LT8500 controls 48 pulse width modulated
(PWM[48:1]) outputs, suitable for control applications
such as driving three LT3595A LED drivers. The chip’s
operation is best understood by referring to the Block
Diagram in Figure 1.
The major blocks inside the LT8500 are: a 584-bit shift
register (SR[0:583]), 48 6-bit correction registers
(COR[1:48]), a correction multiplier, 48 PWM channels
and a PWMCK clock counter. Each PWM channel stores
data for the associated PWMx output pin and includes a
PWM register (PWMR) and a PWM synchronization reg-
ister (PWMRSYNC). The lower 8 bits of the 584-bit shift
register are the command register (CR[0:7]) and the rest
of the shift register contains the frame data.
A comparison of a channel’s PWMRSYNC register to the
PWMCK counter generates the respective PWM output
signal. The input of the 584-bit shift register (SR[0]) is
connected to the SDI signal. SDI is also an input to the
correctionmultiplier.Theoutputofthe584-bitshiftregister
(SR[583]) is connected to SDO.
The user communicates with the part by controlling the
serialinterfacepinsSDI,SCKIandLDIBLANK.Aserialdata
frame, called a command frame, is shifted into the part
on SDI using SCKI as the clock signal. At the same time,
the status frame is shifted out on SDO. A rising edge on
the LDIBLANK pin terminates a frame. A frame consists
of a 12-bit data field for each PWM channel, followed
by an 8-bit command field, totaling (12 × 48) + 8 = 584
bits. The data is transmitted with the most significant
channel first, and each field is transmitted MSB first.
The frame formats and timing are illustrated in Figures 3
and 4, respectively. There are eight commands, two of
which update the PWM[48:1] outputs. The commands are
summarized in Table 2. Within this document, command
frames will be referred to by the commands they issue,
such as “update frame” or “correction frame.”
With a 50MHz SCKI, a single frame can be transmitted in
11.7s (584 SCKIs + LDI), for a frame rate of 85.5kHz.
A 25MHz PWMCK creates a PWM period (4096 PWMCKs)
of 164s, or a PWM output frequency of 6.1kHz.
Update frames are used to serially load the 12-bit values
for each of the 48 PWM channels. The LT8500 contains
a correction multiplier that can automatically scale the
12-bit PWM channel data before it’s stored. By default,
the correction multiplier is enabled and scales incoming
channel data according to:
PWMOUTn = CHANn(NOM)
2
3
CORn + 32
64
where PWMOUTn is the number of PWMCK cycles that
PWMn is high, CHANn(NOM) is the nth channel field in
the frame, and CORn is the nth programmed correction
setting (CORn = 0 to 63). See Table 1 for examples.
Otherwise, when the correction multiplier is disabled, the
incoming data is stored unchanged:
PWMOUTn = CHANn(NOM)
The correction multiplier is disabled by the correction reg-
ister disable bit (CRD), which is toggled by the correction
toggle command (CMD = 0x7X). By default, the correction
multiplier is enabled after power-up and the CRD bit is low.
The result generated by the correction multiplier moves
to the respective PWMRSYNC register after an update
frame. An update frame does this either synchronously
or asynchronously. A synchronous update frame will copy
the data to the PWMR on the subsequent rising edge of
LDI which marks the end of the frame, and then from the
PWMR to the PWMRSYNC register at the beginning of a
PWM period. A PWM period starts when the free-running
PWMCK counter is zero. Otherwise, the asynchronous
update frame will copy the data from the correction mul-
tiplier, through the PWMR to the PWMRSYNC at the same
time, on the subsequent rising edge of LDI which marks
the end of the frame.
As soon as the PWMRSYNC registers are updated with
their new values, the PWM outputs will reflect the update.
As mentioned earlier, the PWMR outputs are generated
by comparing the respective PWMRSYNC values to the
PWMCK counter.
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