參數(shù)資料
型號: LT6700-1
廠商: Linear Technology Corporation
英文描述: Micropower, Low Voltage, SOT-23, Dual Comparator with 400mV Reference
中文描述: 微功耗,低電壓,采用SOT - 23,雙400mV的參考與比較
文件頁數(shù): 11/12頁
文件大?。?/td> 237K
代理商: LT6700-1
LT6700-1/LT6700-2/LT6700-3
11
6700123fb
APPLICATIU
W
U
U
LT6700-1
V
S
10k
GND
1
5
+INA
–INB OUTB
OUTA
2
6
3
4
100k*
100k*
0.22
μ
F
+
V
IN
412k*
10k**
470
Lithium
COIN CELL
10k
10k
750
10k
750**
1
3V/5V
3V/5V
Σ
SAMPLE
IN
MOC-207
MOC-207**
PWM OUT
(OR
Σ
SENSE)
2
1
5
6
5
6
2
0.1
μ
F
0.1
μ
F
3V NOM (I
S
< 3mA)
5 V
REF
= 2V
6700123 F03
22
μ
F
1% METAL FILM
DELETE FOR PWM MODE
CONNECT FOR PWM MODE
OPTIMIZED FOR 2kHz
Σ
SAMPLING, f
PWM(MAX)
0.6kHz
*
**
309k*
NC7S14
309k*
0V TO 2V
+
Figure 3. Isolated PWM or
Σ
Converter
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
APPLICATIU
W
U
U
ence, rather like an isolated instrumentation amplifier. The
section B comparator is used to generate a 2V reference
supply level for the CMOS NOT gate (inverter), which
serves as the precision switch element for the charge
balancer. The heart of the charge balancer is the section A
comparator, which is detecting slight charge or discharge
states on the 0.22
μ
F “integration” capacitor as it remains
balanced at
400mV by feedback through the NOT gate.
The input sense voltage, V
IN
, is converted to an imbalance
current that the NOT gate duty cycle is continually correct-
ing for, thus the digital waveform at the section A com-
parator output is a PWM representation of V
IN
with respect
to the 2V “full scale.” In this particular circuit, the PWM
information drives the LED of an optocoupler, allowing the
V
IN
information to be coupled across a dielectric barrier.
As an additional option to the circuit, the feedback loop can
be broken and a second optocoupler employed to provide
the charge balance management. This configuration al-
lows for clocking the comparator output (externally to this
circuit) and providing synchronous feedback such that a
simple
Σ
voltage-to-frequency conversion can be formed
if desired. Approximately 11-bit accuracy and noise per-
formance was observed in a one second integration period
for duty factors from 1% to 99%.
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