minimized by connecting the VREF <" />
參數(shù)資料
型號(hào): LT6556IGN#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 16/16頁(yè)
文件大?。?/td> 0K
描述: IC VIDEO MULTIPLEXER 2X1 24SSOP
標(biāo)準(zhǔn)包裝: 2,500
功能: 視頻多路復(fù)用器
電路: 3 x 2:1
電壓電源: 雙電源
電壓 - 電源,單路/雙路(±): ±2.25 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
LT6556
9
6556f
To improve clamping, the pin’s DC impedance should be
minimized by connecting the VREF pin directly to ground
in the symmetric dual supply case with a common mode
voltage of 0V. If the common mode voltage is not centered
at ground or the input voltage exceeds plus or minus three
diodes from ground, an external resistor to either supply
can be added to shift the VREF voltage to the desired level.
The only way to cover the full input voltage range of V+
1V to V+ – 1V is to shift VREF up or down.
The VREF pin can also be directly driven with a DC source.
Figure 2 shows the effect of the clamp on input current
when sweeping input voltage with various VREF pin volt-
ages. Bypassing the VREF pin is not necessary.
INPUT VOLTAGE (V)
–4
INPUT
CURRENT
(
μ
A)
0
100
4
6556 F02
–100
–250
–200
–2
0
2
–3
–1
1
3
250
200
–50
50
–150
150
TA = 25°C
VS = ±5V
VREF = 2V
VREF = 1V
VREF = 0V
VREF = –1V
VREF = –2V
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to less
than ±10mA. Continuing to drive the input beyond the
output limit can result in increased current drive and
slightly increased swing, but will also increase supply
current and may result in delays in transient response
at larger levels of overdrive.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
benet from the very high speed and very low crosstalk of
the LT6556. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input traces must be run over a distance of
several centimeters, they should use a controlled imped-
ance with either series or shunt terminations (nominally
50Ω or 75Ω) to maintain signal delity.
Care should be taken to minimize capacitance on the
LT6556’s output traces by increasing spacing between
traces and adjacent metal and by eliminating metal planes
in underlying layers. To drive cable or traces longer than
several centimeters, using the LT6555 with its xed gain
of+2 in conjunction with series and load termination resis-
tors may provide better results.
A plot of AC performance driving a 1k load with various
trace lengths is shown in Figure 3. All data is from a 4-layer
board with 2oz copper, 18mil of board layer thickness to
the ground plane, a trace width of 12mils and spacing to
adjacent metal of 18mils. The 0.2cm output trace places
the 1k resistor as close to the part as possible, while the
other curves show the load resistor consecutively further
away. The worst case, 4cm, trace has almost 10pF of
parasitic capacitance.
FREQUENCY (MHz)
0.1
AMPLITUDE
(dB)
6
4
2
0
–2
–4
–6
1
10
100
1000
6556 F03
4cm TRACE
0.2cm TRACE
2cm TRACE
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
Figure 3. Response vs Output Trace Length
APPLICATIO S I FOR ATIO
WU
U
Figure 2. Input Current vs Input Voltage
at Different VREF Voltages
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