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參數(shù)資料
| 型號： | LT6200CS8-10#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 1.6GHZ R-R I/O 8-SOIC |
| 標準包裝： | 2,500 |
| 放大器類型： | 緩沖器 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 450 V/µs |
| 增益帶寬積： | 1.6GHz |
| 電流 - 輸入偏壓： | 23µA |
| 電壓 - 輸入偏移： | 2500µV |
| 電流 - 電源： | 20mA |
| 電流 - 輸出 / 通道： | 90mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 12.6 V，±1.25 V ~ 6.3 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
21
62001ff
LT6200/LT6200-5
LT6200-10/LT6201
Figure 2 shows the input and output waveforms of the
LT6200 driven into clipping while connected in a gain of
AV = 1. In this photo, the input signal generator is clipping
at±35mA,andtheoutputtransistorssupplythisgenerator
current through the protection diodes.
applicaTions inForMaTion
15MHz/DIV
100kHz
150kHz
0V
VCC
2.5V
VEE
–2.5V
6200 F02
Figure 2. VS = ±2.5V, AV = 1 with Large Overdrive
ESD
The LT6200 has reverse-biased ESD protection diodes on
all inputs and outputs, as shown in Figure 1. If these pins
are forced beyond either supply, unlimited current will
flow through these diodes. If the current is transient and
limitedto30mAorless,nodamagetothedevicewilloccur.
Noise
The noise voltage of the LT6200 is equivalent to that of
a 56Ω resistor—and for the lowest possible noise, it is
desirable to keep the source and feedback resistance
at or below this value (i.e., RS + RG//RFB ≤ 56Ω). With
RS + RG//RFB = 56Ω the total noise of the amplifier is:
en = √(0.95nV)2 + (0.95nV)2 = 1.35nV. Below this resis-
tance value the amplifier dominates the noise, but in the
resistance region between 56Ω and approximately 6kΩ,
the noise is dominated by the resistor thermal noise. As
the total resistance is further increased, beyond 6k, the
noise current multiplied by the total resistance eventually
dominates the noise.
For a complete discussion of amplifier noise, see the
LT1028 data sheet.
Power Dissipation
The LT6200 combines high speed with large output cur-
rent in a small package, so there is a need to ensure that
the die’s junction temperature does not exceed 150°C.
The LT6200 is housed in a 6-lead TSOT-23 package. The
package has the V– supply pin fused to the lead frame to
enhance the thermal conductance when connecting to a
ground plane or a large metal trace. Metal trace and plated
through-holescanbeusedtospreadtheheatgeneratedby
the device to the backside of the PC board. For example,
on a 3/32" FR-4 board with 2oz copper, a total of 270mm2
connects to Pin 2 of the LT6200 (in a TSOT-23 package)
bringing the thermal resistance,
θJA, to about 135°C/W.
Without an extra metal trace beside the power line con-
necting to the V– pin to provide a heat sink, the thermal
resistance will be around 200°C/W. More information on
thermal resistance with various metal areas connecting
to the V– pin is provided in Table 1.
Table 1. LT6200 6-Lead TSOT-23 Package
COPPER AREA
TOPSIDE (mm2)
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
270
2500
135C/W
100
2500
145C/W
20
2500
160C/W
0
2500
200C/W
Device is mounted on topside.
Junction temperature TJ is calculated from the ambient
temperature TA and power dissipation PD as follows:
TJ = TA + (PD θJA)
The power dissipation in the IC is the function of the sup-
ply voltage, output voltage and the load resistance. For
a given supply voltage, the worst-case power dissipation
PD(MAX) occurs at the maximum quiescent supply current
and at the output voltage which is half of either supply
voltage (or the maximum swing if it is less than half the
supply voltage). PD(MAX) is given by:
PD(MAX) = (VS IS(MAX)) + (VS/2)2/RL
Example: An LT6200 in TSOT-23 mounted on a 2500mm2
area of PC board without any extra heat spreading plane
connected to its V– pin has a thermal resistance of
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