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LT4430
8
4430f
S U
APPLICATIO
The LT4430 incorporates a unique overshoot control
function that allows the user to ramp the output voltage
on startup and recovery from short-circuit conditions,
preventing overshoot. A capacitor, connected from the OC
pin to GND and charged by internal 8.5μA current source
I
OC
, sets the ramp rate. On startup, Q1 actively holds the
OC capacitor low until V
IN
of the LT4430 reaches its typi-
cal undervoltage lockout threshold of 2.2V. Q1 then turns
off and the OC capacitor charges linearly. Q2 and Q3 OR
the OC pin voltage and the 600mV reference voltage at
the non-inverting terminal of the error amplifier. The OC
pin voltage is the reference voltage for the error amplifier
until it increases above 600mV. If the feedback loop is in
control, the FB pin voltage follows and regulates to the OC
pin voltage. As the OC pin voltage increases past 600mV,
the reference voltage takes control of the error amplifier
and the FB pin regulates to 600mV. The OC pin voltage
increases until it is internally clamped by R2, Q6 and V1.
The OC pin’s typical clamp voltage of 0.93V ensures that
Q3 turns off. All of I1’s current flows in Q2, matching I2’s
current in Q4.
In a short-circuit condition, the output voltage decreases to
something well below the regulated level. The error ampli-
fier reacts by increasing the COMP pin voltage, thereby
decreasing the drive to the optocoupler. The decreased
optocoupler bias signals the primary-side controller to
increase the amount of power it delivers in an attempt
to raise the output voltage back to its regulated value. As
long as the fault persists, the output voltage remains low.
The error amplifier’s COMP pin voltage increases until it
reaches a clamp level set by Q7 and V2. Q7’s resultant
collector current drives internal logic that closes normally
open switch S1. This action activates the overshoot control
amplifier which employs a unity-gain follower configura-
tion. The overshoot control amplifier monitors the FB pin
voltage and, on S1’s closing, pulls the OC pin voltage
down to the FB pin voltage plus a built-in offset voltage
of typically 48mV. The built-in offset voltage serves two
W
U
U
purposes. First, the offset voltage prevents the overshoot
control amplifier from interfering with normal transient
operating conditions. Second, the offset voltage biases
the feedback loop so that if the short-circuit condition
ends, the feedback loop immediately starts to increase
the output voltage to its regulated value.
If the fault condition ceases, the output voltage increases.
In response, the error amplifier COMP pin’s voltage
decreases. This action opens switch S1, deactivates the
overshoot control amplifier and allows the OC pin capacitor
to charge. The FB pin voltage increases quickly until the
FB pin voltage exceeds the OC pin voltage. The feedback
loop increases the drive to the optocoupler until the FB
pin follows and regulates to the OC pin voltage. Again, as
the OC pin voltage increases past 600mV, the reference
voltage takes control of the error amplifier and the FB pin
regulates to 600mV.
Generating a V
IN
Bias Supply
Biasing an LT4430 is crucial to proper operation. If the
overshoot control (OC) function is not being used and the
output voltage is greater than 3.3V, the IC may be biased
from V
OUT
. In these cases, it is the user’s responsibility to
verify large-signal startup and fault recovery behavior.
If the overshoot control function is being used or the
output voltage is below the LT4430’s minimum operat-
ing voltage of 3V, employing an alternate bias method is
necessary. The LT4430’s undervoltage lockout (UVLO)
circuitry, controlled by V
IN
, resets and holds the OC pin
capacitor low for V
IN
less than 2.2V. When V
IN
increases
above 2.2V, the circuit releases the OC pin capacitor. The
LT4430’s supply voltage must come up faster than the
ouput voltage to assert loop control and limit output volt-
age overshoot. In most cases, a few simple components
accomplish this task. Adding a few biasing components
to control overshoot is advantageous. Let’s examine bias
circuits for different topologies.