參數(shù)資料
型號(hào): LT4250H
廠(chǎng)商: Linear Technology Corporation
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: Negative 48V Hot Swap Controller
中文描述: 負(fù)48V熱插拔控制器
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 230K
代理商: LT4250H
5
LT4250L/LT4250H
4250lhf
PI
FU
CTIO
N
S
U
U
OV
(Pin 2):
Analog Overvoltage Input. When OV is pulled
above the 1.255V threshold, an overvoltage condition is
detected and the GATE pin will be immediately pulled low.
The GATE pin will remain low until OV drops below the
1.235V threshold.
UV (Pin 3):
Analog Undervoltage Input. When UV is
pulled below the 1.125V threshold, an undervoltage
condition is detected and the GATE pin will be immedi-
ately pulled low. The GATE pin will remain low until UV
rises above the 1.255 threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur. The response
time for this pin is 1.5
μ
s. Add an external capacitor to this
pin for additional filtering.
V
EE
(Pin 4):
Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5):
Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and
SENSE, the overcurrent condition will pull down the
GATE pin and regulate the voltage across the resistor to
be 50mV. If the overcurrent condition exists for more
than 500
μ
s the electronic circuit breaker will trip and turn
off the external MOSFET.
If the current limit value is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
current limit feature, V
EE
and SENSE can be shorted
together.
GATE (Pin 6):
Gate Drive Output for the External
N-Channel MOSFET. The GATE pin will go high when the
following start-up conditions are met: the UV pin is high,
the OV pin is low, (V
SENSE
– V
EE
) < 50mV and the V
DD
pin
is greater than V
UVLOH
. The GATE pin is pulled high by a
45
μ
A current source and pulled low with a 50mA current
source. During current limit the GATE pin is pulled low
using a 100mA current source.
DRAIN (Pin 7):
Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel MOSFET and the
V
pin of the power module. When the DRAIN pin is
below V
DL
, the PWRGD/PWRGD pin will latch to indicate
the switch is on.
V
DD
(Pin 8):
Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. An undervoltage lockout
circuit disables the chip until the V
DD
pin is greater than
the 16V V
UVLOH
threshold.
BLOCK DIAGRA
+
+
+
+
DRAIN
4250 BD
GATE
SENSE
V
EE
V
EE
V
DL
OUTPUT
DRIVE
PWRGD/PWRGD
50mV
V
CC
V
DD
REF
REF
UV
OV
LOGIC
V
AND
REFERENCE
GENERATOR
+
+
+
+
V
GATE
V
GH
500
μ
s
DELAY
GATE
DRIVER
UVLO
相關(guān)PDF資料
PDF描述
LT4250HCN8 Negative 48V Hot Swap Controller
LT4250HCS8 Negative 48V Hot Swap Controller
LT4250L Negative 48V Hot Swap Controller
LT4250LCN8 Negative 48V Hot Swap Controller
LT4250LCS8 Negative 48V Hot Swap Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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