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參數(shù)資料
| 型號(hào)： | LT3845EFE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 263K |
| 代理商： | LT3845EFE#TR |
LT3845
6
3845fb
PIN FUNCTIONS
VIN (Pin 1): The VIN pin is the main supply pin and should
be decoupled to SGND with a low ESR capacitor (at least
0.1μF) located close to the pin.
SHDN (Pin 2): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
used to implement an undervoltage lockout (UVLO) circuit.
See Application Information section for implementing a
UVLO function. When the SHDN pin is pulled below a
transistor VBE (0.7V), a low current shutdown mode is
entered, all internal circuitry is disabled and the VIN supply
current is reduced to approximately 9μA. Typical pin input
bias current is <10nA and the pin is internally clamped to
6V. If the function is not used, this pin may be tied to VIN
through a high value resistor.
CSS (Pin 3): The soft-start pin is used to program the
supply soft-start function. Use the following formula to
calculate CSS for a given output voltage slew rate:
CSS = 2μA(tSS/1.231V)
The pin should be left unconnected when not using the
soft-start function.
BURST_EN (Pin 4): Burst Mode Operation Enable Pin. This
pin also controls reverse-current inhibit mode of operation.
When the pin voltage is below 0.5V, Burst Mode operation
and reverse-current inhibit functions are enabled. When
the pin voltage is above 0.5V, Burst Mode operation is dis-
abled, but reverse-current inhibit operation is maintained.
In this mode of operation (BURST_EN = VFB) there is a
1mA minimum load requirement. Reverse-current inhibit
is disabled when the pin voltage is above 2.5V. This pin is
typically shorted to ground to enable Burst Mode operation
and reverse-current inhibit, shorted to VFB to disable Burst
Mode operation while enabling reverse-current inhibit,
and connected to VCC pin to disable both functions. See
Applications Information section.
VFB (Pin 5): The output voltage feedback pin, VFB, is
externally connected to the supply output voltage via a
resistive divider. The VFB pin is internally connected to
the inverting input of the error amplier. In regulation,
VFB is 1.231V.
VC (Pin 6): The VC pin is the output of the error ampli-
er whose voltage corresponds to the maximum (peak)
switch current per oscillator cycle. The error amplier is
typically congured as an integrator by connecting an RC
network from the VC pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Specic integrator characteristics can be congured to
optimize transient response. When Burst Mode operation
is enabled (see Pin 4 description), an internal low imped-
ance clamp on the VC pin is set at 100mV below the burst
threshold, which limits the negative excursion of the pin
voltage. Therefore, this pin cannot be pulled low with a
low impedance source. If the VC pin must be externally
manipulated, do so through a 1kΩ series resistance.
SYNC (Pin 7): The Sync pin provides an external clock
input for synchronization of the internal oscillator. RSET
is set such that the internal oscillator frequency is 10%
to 25% below the external clock frequency. If unused the
Sync pin is connected to SGND. For more information see
“Oscillator Sync” in the Application Information section
of this datasheet.
fSET (Pin 8): The fSET pin programs the oscillator frequency
with an external resistor, RSET. The resistor is required
even when supplying external sync clock signal. See the
Applications Information section for resistor value selec-
tion details.
SENSE– (Pin 9):
The SENSE– pin is the negative input for
the current sense amplier and is connected to the VOUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to ±100mV across the
SENSE inputs.
SENSE+ (Pin 10):
The SENSE+ pin is the positive input for
the current sense amplier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to ±100mV across
the SENSE inputs.
PGND (Pin 11): The PGND pin is the high-current ground
reference for internal low side switch driver and the VCC
regulator circuit. Connect the pin directly to the negative
terminal of the VCC decoupling capacitor. See the Applica-
tion Information section for helpful hints on PCB layout
of grounds.
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