參數(shù)資料
型號(hào)： LT3758MPMSE#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO10
封裝： 3 X 3 MM, LEAD FREE, PLASTIC, MSOP-10
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 554K
代理商： LT3758MPMSE#PBF
LT3758
19
3758fc
ApplicAtions inForMAtion
Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The transformer design for discontinuous mode of opera-
tion is chosen as presented here. According to Figure 8,
the minimum D3 (D3MIN) occurs when the the converter
has the minimum VIN and the maximum output power
(POUT). Choose D3MIN to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation. Choosing higher D3 allows the use of
low inductances but results in higher switch peak current.
The user can choose a DMAX as the start point. Then, the
maximum average primary currents can be calculated by
the following equation:
ILP(MAX) =ISW(MAX) =
POUT(MAX)
DMAX VIN(MIN) η
where
h is the converter efficiency.
If the flyback converter has multiple outputs, POUT(MAX)
is the sum of all the output power.
The maximum average secondary current is:
ILS(MAX) =ID(MAX) =
IOUT(MAX)
D2
where
D2 = 1 – DMAX – D3
the primary and secondary RMS currents are:
ILP(RMS) = 2ILP(MAX)
DMAX
3
ILS(RMS) = 2ILS(MAX)
D2
3
According to Figure 8, the primary and secondary peak
currents are:
ILP(PEAK) = ISW(PEAK) = 2 ILP(MAX)
ILS(PEAK) = ID(PEAK) = 2 ILS(MAX)
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
LP =
D2MAX V
2
IN(MIN) η
2 POUT(MAX) f
LS =
D22 (VOUT + VD)
2 IOUT(MAX) f
The primary to second turns ratio is:
NP
NS
=
LP
LS
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
MOSFET turn-off. This is increasingly prominent at higher
load currents, where more stored energy must be dis-
sipated. In some cases a snubber circuit will be required
to avoid overvoltage breakdown at the MOSFET’s drain
node. There are different snubber circuits, and Application
Note 19 is a good reference on snubber design. An RCD
snubber is shown in Figure 7.
The snubber resistor value (RSN) can be calculated by the
following equation:
RSN = 2
V2SN VSN VOUT
NP
NS
I2SW(PEAK) LLK f
where VSN is the snubber capacitor voltage. A smaller
VSN results in a larger snubber loss. A reasonable VSN is
2 to 2.5 times of:
VOUT NP
NS
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