LT3758
24
3758fc
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an inverting
converteraresimilartothoseoftheSEPICconverter.Please
refer to the corresponding SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
outputcapacitorsarecontinuous.Theoutputripplevoltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
VOUT(P–P) = IL2 ESRCOUT +
1
8 f COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 IL2
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 10) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX)
DMAX
1
DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high speed operation of the LT3758 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3758 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
In boost configuration, the high di/dt loop contains
the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.
In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and the sensing resistor. The high di/
dt secondary loop contains the output capacitor, the
secondary winding and the output diode.
In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
ApplicAtions inForMAtion