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參數(shù)資料
| 型號(hào)： | LT3724 |
| 廠商： | Linear Technology Corporation |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 抗輻射高效，5安培開(kāi)關(guān)穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 16/24頁(yè) |
| 文件大?。?/td> | 240K |
| 代理商： | LT3724 |
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LT3724
16
3724f
The desired soft-start rise time (t
SS
) is programmed via a
programming capacitor C
SS1
, using a value that corre-
sponds to 2
μ
A average current during the soft-start inter-
val. This capacitor value follows the relation:
C
t
V
SS
SS
OUT
1
6
2 10
=
–
R
SS
is typically set to 200k for most applications.
Considerations for Low-Voltage Output Applications
The LT3724 C
SS
pin biases to 220mV during the soft-start
cycle, and this voltage is increased at Figure 4 node “A” by
the 2
μ
A signal current through R
SS
, so the output has to
reach this value before the soft-start function is engaged.
The value of this output soft-start startup voltage offset
(V
OUT(SS)
) follows the relation:
V
OUT(SS)
= 220mV + R
SS
2 10
–6
Which is typically 0.64V for R
SS
= 200k.
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start startup voltage
offset. This is possible by reducing the value of R
SS
. With
reduced values of R
SS
, the signal component caused by
voltage ripple on the output must be minimized for proper
soft-start operation.
Peak-to-peak output voltage ripple (
V
OUT
) will be im-
posed on node “A” through the capacitor C
SS1
. The value
of R
SS
can be set using the following equation:
R
V
SS
OUT
=
.
1 3 10
6
–
It is important to use low ESR output capacitors for
LT3724 voltage converter designs to minimize this ripple
voltage component. A design with an excessive ripple
component can be evidenced by observing the V
C
pin
during the start cycle.
The soft-start cycle should be evaluated to verify that the
reduced R
SS
value allows operation without excessive
modulation of the V
C
pin before finalizing the design.
If V
C
pin has an excessive ripple component during
the soft-start cycle, converter output ripple should be
reduced. This is typically accomplished by increasing
output capacitance and/or reducing output capacitor ESR.
External Current Limit Foldback Circuit
An additional startup voltage offset can occur during the
period before the LT3724 soft-start circuit becomes ac-
tive. Before the soft-start circuit throttles back the V
C
pin
in response to the rising output voltage, current as high as
the peak programmed current limit (I
MAX
) can flow in the
switched inductor. Switching will stop once the soft-start
circuit takes hold and reduces the voltage on the V
C
pin,
but the output voltage will continue to increase as the
stored energy in the inductor is transferred to the output
capacitor. With I
MAX
in the inductor, the resulting leading-
edge rise on V
OUT
due to energy stored in the inductor
follows the relation:
V
I
L
C
OUT
MAX
OUT
=
/ 2
APPLICATIOU
W
U
U
Figure 5. Soft-Start Characteristic
Showing Excessive Ripple Component
Figure 6. Desirable Soft-Start Characteristic
TIME, 250 s/DIV
3724F06
V(V
C
)
V
OUT(SS)
V
OUT
TIME, 250
μ
s/DIV
V(V
C
)
V
OUT(SS)
V
OUT
3724F05
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| LT3724EFE#TRPBF | 功能描述:IC REG CTRLR BST INV PWM 16TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無(wú) 升壓:是 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤(pán) 包裝:帶卷 (TR) |
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