參數(shù)資料
型號: LT3694IFE-1#TRPBF
廠商: Linear Technology
文件頁數(shù): 18/28頁
文件大?。?/td> 338K
描述: IC REG TRPL BUCK/LINEAR 20TSSOP
標準包裝: 2,500
拓撲: 降壓(降壓)(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關: 250kHz ~ 2.5MHz
電壓/電流 - 輸出 1: 0.75 V ~ 16 V,2.6A
電壓/電流 - 輸出 2: 控制器
電壓/電流 - 輸出 3: 控制器
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 4 V ~ 36 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)裸露焊盤
供應商設備封裝: 20-TSSOP-EP
包裝: 帶卷 (TR)
LT3694/LT3694-1
18
36941fb
The LDO may be shut down if it is unused by pulling the
FB pin up with a resistor that will source at least 30糀. The
FB pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3694 outputs provided that channel is
always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 1.8V above the LDO DRIVE
voltage, otherwise the NPN base current comes from V
IN
.
The base drive current is limited to 15mA.
LDO FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (refer to the Block Diagram in
Figure 7) between the emitter of the external NPN pass
resistor and the feedback pin, FB2 or FB3. Choose the
resistors according to:
 
R1=R2
V
OUT
0.75
1
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
APPLICATIONS INFORMATION
LDO Current Limit
The LDO has a current limit available to reduce the power
consumption of the NPN transistor under overload condi-
tions. The current limit requires the NPN transistor collector
to be connected to the BIAS pin through a low resistance
sense resistor. The current limit circuit senses the voltage
drop across this resistor and reduces the base drive cur-
rent when the limit voltage exceeds 60mV. This will limit
the output current to 60mV/R
SENSE
.
If the overload causes the output voltage to drop, the limit
voltage is folded back to reduce power in the NPN transis-
tor. The limit circuit monitors the FB voltage and ramps
the limit voltage down once V
FB
 drops to 0.6V. The limit
voltage will fold back to 26mV when V
FB
 has dropped to
0V. The current foldback is disabled until the associated
TRK/SS pin rises above 0.68V. This insures proper start-up
under full load conditions. Figure 7 shows the LDO circuit
with current limit.
Properly routing the current limit sense resistors is critical
to minimize errors in the current limit. The sense con-
nections are the BIAS pin (both channels) on the high
side and LIM2 or LIM3 on the bottom side. These sense
leads must be routed separately from all current carrying
traces. Figure 9 shows a layout that minimizes trace re-
sistance errors. The current limit sense resistors (RLIM2
and RLIM3) are placed close together and the BIAS pin
trace is connected to V
OUT1
 at their junction. The bottom
sides of these resistors have a separate via and trace to
the LIM2 and LIM3 pins.
The foldback can dramatically reduce the power dissipation
of the NPN pass transistor under short-circuit conditions.
For example, an application that has V
OUT1
= 3.3V and
V
OUT2
= 2.5V will nominally have 0.8V across the pass
transistor V
CE
. Under short-circuit conditions, the pass
transistor V
CE
 will increase to 3.3V. Without foldback the
power dissipation in the pass transistor will increase by
more than 4x, but with foldback the power dissipation
only increases by 78%.
FB2
R1
OUT1
OUT2
R2
0.75V
DRV2
LIM2
BIAS
60mV
LT3694

+

+
36941 FO7
R
SENSE
Figure 7. LDO with Current Limit
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