參數(shù)資料
型號(hào)： LT3682EDD#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PDSO12
封裝： 3 X 3 MM, LEAD FREE, PLASTIC, DFN-12
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 253K
代理商： LT3682EDD#PBF
LT3682
17
3682f
APPLICATIONS INFORMATION
5μs/DIV
VOUT
20mV/DIV
IL
0.2A/DIV
VSW
5V/DIV
3682 F04
VIN = 12V; FRONT PAGE APPLICATION
ILOAD = 5mA
Figure 4. Burst Mode Operation
3682 F03
ILOAD
0.5A/DIV
VOUT
100mV/DIV
20μs/DIV
Figure 3. Transient Load Response of the LT3682.
3.3VOUT Typical Application with VIN = 12V as the
Load Current is Stepped from 300mA to 650mA.
capacitor on the VC pin (CC) integrates the error amplier
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor RC in series with CC.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (CPL) across the feedback divider may improve
the transient response. Figure 3 shows the transient
response when the load current is stepped from 300mA
to 650mA and back to 300mA.
the output power is delivered to the load by the output
capacitor. Because the LT3682 delivers power to the output
with single, low current pulses, the output ripple is kept
below 15mV for a typical application. In addition, VIN and
BD quiescent currents are reduced to typically 35μA and
55μA respectively during the sleep time. As the load current
decreases towards a no load condition, the percentage of
time that the LT3682 operates in sleep mode increases and
the average input current is greatly reduced resulting in
high efciency even at very low loads. (See Figure 4). At
higher output loads (above about 70mA for the front page
application) the LT3682 will be running at the frequency
programmed by the RT resistor, and will be operating in
standard PWM mode. The transition between PWM and
Low Ripple Burst Mode is seamless, and will not disturb
the output voltage.
If low quiescent current is not required, tie SYNC high to
select pulse-skip mode. The benet of this mode is that the
LT3682 will enter full frequency standard PWM operation at
a lower output load current than when in Burst Mode. The
front page application circuit will switch at full frequency
at output loads higher than about 30mA. The maximum
load current that the LT3682 can supply is reduced when
SYNC is high.
Low Ripple Burst Mode and Pulse-Skip Mode
The LT3682 is capable of operating in either Low Ripple Burst
Mode or Pulse-Skip Mode which are selected using the SYNC
pin. See the Synchronization section for more information.
To enhance efciency at light loads, the LT3682 can be
operated in Low Ripple Burst Mode operation which keeps
the output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst Mode
operation, the LT3682 delivers single cycle bursts of current
to the output capacitor followed by sleep periods where
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