參數(shù)資料
型號(hào)： LT3641EUFD#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 3.4 A DUAL SWITCHING CONTROLLER, 2350 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28
文件頁(yè)數(shù)： 11/28頁(yè)
文件大小： 416K
代理商： LT3641EUFD#TRPBF
LT3641
19
3641f
Figure 7. PFM Operation
500ns/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3641 F08a
VIN = 12V
VOUT1 = 3.3V/25mA
VIN2 = VOUT1
VOUT2 = 1.8V/30mA
2μs/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3641 F08b
VIN = 12V
VOUT1 = 3.3V/25mA
VIN2 = VOUT1
VOUT2 = 1.8V/20mA
2μs/DIV
IL1
0.5A/DIV
SW1
10V/DIV
IL2
0.5A/DIV
SW2
5V/DIV
3641 F08c
VIN = 12V
VOUT1 = 3.3V/0mA
VIN2 = VOUT1
VOUT2 = 1.8V/30mA
(7a)
(7b)
(7c)
Power-On Reset Timer
Each channel of the LT3641 has a power-on comparator.
Both comparators are enabled when the LT3641 is powered
up and starts monitoring their corresponding feedback
voltages. The threshold of power-on comparator is 1.15V
for the high voltage channel, and 550mV for the low
voltage channel.
Both RST1 and RST2 are open-drain outputs with weak
internal pull-ups (100k to ~2V). The DC characteristics of
the RST1 and RST2 pull-down strength are shown in the
Typical Performance Characteristics section. The weak
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
conguration allows wired-OR connections.
The two power-on reset timers share one oscillator. The
power-on reset timeout period, t RST (64 cycles on the
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, CPOR, between
the CPOR pin and ground:
tRST = CPOR 37 10
6
s
F
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t RST will be
limited by the accuracy and temperature coefcient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
pin, such as probe capacitance, can affect t RST.
Watchdog
The WDE pin is the enable pin for the watchdog. As soon as
RST2 is released, the watchdog starts a delay period, tDLY,
during which the input signal at the WDI pin is ignored for
higher reliability. After the delay period, the watchdog starts
detecting falling edges on the WDI pin. If the time between
any two WDI falling edges is shorter than the watchdog
lower boundary, tWDL, or longer than the watchdog upper
boundary, tWDU, the WDO pin is pulled down for a period
of t RST, which is the same as the power-on reset timeout
period. When the WDO pin is released, the watchdog again
starts the delay period.
APPLICATIONS INFORMATION
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