參數(shù)資料
型號(hào): LT3581IMSE#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PDSO16
封裝: LEAD FREE, PLASTIC, MSOP-16
文件頁(yè)數(shù): 16/36頁(yè)
文件大小: 498K
代理商: LT3581IMSE#TRPBF
LT3581
3581f
Minimum Inductance
Although there can be a tradeoff with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance: (1) provid-
ing adequate load current, (2) avoidance of subharmonic
oscillations and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator.
Adequate Load Current
Smallvalueinductorsresultinincreasedripplecurrentsand
thus, due to the limited peak switch current, decrease the
average current that can be provided to the load. In order
to provide adequate load current, L should be at least:
L
DC V
V
f
I
V
I
BOOST
IN
CESAT
OSC
PK
OUT
OU
>
(
)
2
|
TT
IN
DUAL
IN
CESAT
OSC
V
or
L
DC V
V
f
>
(
)
η
2
II
V
I
V
I
PK
OUT
IN
OUT
|
η
Boost
Topology
SEPIC
or
Inverting
Topologies
where:
LBOOST = L1 for Boost Topologies (see Figure 5)
LDUAL = L1 = L2 for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
LDUAL = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
DC
= Switch Duty Cycle (see Power Switch Duty
Cycle section in Appendix)
IPK
= Maximum Peak Switch Current; should not
exceed 3.3A for a combined SW1 + SW2
current, or 1.9A of SW1 current if SW1 is
being used by itself.
η
= Power Conversion Efficiency (typically 88%
for Boost and 75% for Dual Inductor
Topologies at High Currents)
fOSC
= Switching Frequency
IOUT
= Maximum Output Current
appenDix
Negative values of LBOOST or LDUAL indicate that the out-
put load current, IOUT, exceeds the switch current limit
capability of the LT3581.
Avoiding Sub-Harmonic Oscillations
The LT3581’s internal slope compensation circuit will
prevent sub-harmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the
inductance exceeds a certain minimum value. In applica-
tions that operate with duty cycles greater than 50%, the
inductance must be at least:
L
V
DC
A f
DC
MIN
IN
CESAT
OSC
=
(
)
(
)
(
)
2
1
2 2
1
.
where:
LMIN = L1 for Boost Topologies (see Figure 5)
LMIN = L1 = L2 for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
LMIN = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
Maximum Inductance
Excessive inductance can reduce ripple current to levels
thataredifficultforthecurrentcomparator(A4intheBlock
Diagram) to cleanly discriminate, causing duty cycle jitter
and/or poor regulation. The maximum inductance can be
calculated by:
L
V
mA
DC
f
MAX
IN
CESAT
OSC
=
350
where:
LMAX = L1 for Boost Topologies (see Figure 5)
LMAX = L1 = L2 for Coupled Dual Inductor
Topologies (see Figures 6 and 7)
LMAX = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figures 6 and 7)
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