參數(shù)資料
型號: LT3581EMSE#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PDSO16
封裝: LEAD FREE, PLASTIC, MSOP-16
文件頁數(shù): 9/36頁
文件大小: 498K
代理商: LT3581EMSE#PBF
LT3581
3581f
applicaTions inForMaTion
THERMAL CONSIDERATIONS
Overview
For the LT3581 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed circuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
Power and Thermal Calculations
Power dissipation in the LT3581 chip comes from four
primary sources: switch I2R losses, switch dynamic
losses, NPN base drive DC losses, and miscellaneous
input current losses. These formulas assume continuous
mode operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
The following example calculates the power dissipa-
tion in the LT3581 for a particular boost application
(VIN=5V,VOUT=12V,IOUT=0.83A,fOSC=2MHz,VD=0.45V,
VCESAT = 0.21V).
To calculate die junction temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
TJ = TA + θJA PTOTAL
Table 4. Power Calculations Example for Boost Converter with VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V
DEFINITION OF VARIABLES
EQUATIONS
DESIGN EXAMPLE
VALUE
DC = SWITCH DUTY CYCLE
DC
V
OUT
IN
D
OUT
D
CESAT
=
+
DC
V
=
+
12
5
0 45
12
0 45
0 21
.
– .
DC = 60.9%
IIN = Average Switch Current
η = Power Conversion Efficiency
(typically 88% at high currents)
I
V
I
V
IN
OUT
IN
=
η
I
V
A
V
IN =
12
0 83
5
0 88
.
IIN = 2.3A
PSWDC = Switch I2R Loss (DC)
RSW = Switch Resistance (typically
90mΩ combined SW1 and SW2)
P
DC I
R
SWDC
IN
SW
=
2
P
A
m
SWDC =
0 609 2 3
90
2
.
( . )
PSWDC = 290mW
PSWAC = Switch Dynamic Loss (AC)
P
ns I
V
f
SWAC
IN
OUT
OSC
=
13
P
ns
A
V
MHz
SWAC = (
)
(
)
13
2 3
12
2
.
PSWAC = 718mW
PBDC = Base Drive Loss (DC)
P
V
I
DC
BDC
IN
=
45
P
V
A
BDC =
5
2 3
0 609
45
.
PBDC = 156mW
PINP = Input Power Loss
P
mA V
INP
IN
=
9
P
mA
V
INP =
9
5
PINP = 45mW
PTOTAL = 1.209W
Figure 10. Suggested Component Placement for Dual Inductor
Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.)
Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which
Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
3581 F10
CIN
B
A
C
SYNC
GND
A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN COUT GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR
IMPROVED PERFORMANCE.
COUT
SHDN
CLKOUT
– VOUT
GND
VIN
+
L2
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C1
D1
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