參數(shù)資料
型號(hào)： LT3513IUHF#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 3.5 A SWITCHING REGULATOR, 2220 kHz SWITCHING FREQ-MAX, PQCC38
封裝： 5 X 7 MM, LEAD FREE, PLASTIC, MO-220WHKD, QFN-38
文件頁(yè)數(shù)： 21/22頁(yè)
文件大?。?/td> 374K
代理商： LT3513IUHF#TRPBF
LT3513
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FB5 (Pin 1): Feedback Pin. Tie the resistor tap to this pin
and set the output of the LDO according to VLDO = 0.625
(1 + R14/R15). Reference designators refer to Figure 1.
VC1 (Pin 2): Control Voltage and Compensation Pin for
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 1.
RUN-SS3/4 (Pin 3): Run/Soft-Start Pin. This is the soft-
start pin for switching regulators 3 and 4. Place a soft-start
capacitor here to limit start-up inrush current and output
voltage ramp rate. When the BIAS pin reaches 2.25V, a 2A
current source charges the capacitor. When the voltage at
this pin reaches 0.8V, switches 3 and 4 turn on and begin
switching. For slower start-up use a larger capacitor. For
complete shutdown tie RUN-SS3/4 to ground.
FB3 (Pin 4): Feedback Pin. Tie the resistor tap to this pin
and set VON according to VON = 1.22V (1 + R8/R9) –
150mV. Reference designators refer to Figure 1.
RUN-SS2 (Pin 5): Run/Soft-Start Pin. This is the soft-start
pin for switching regulator 2. Place a soft-start capacitor
here to limit start-up inrush current and output voltage
ramp rate. When the BIAS pin reaches 2.25V, a 2A cur-
rent source charges the capacitor. When the voltage at this
pin reaches 0.8V, switch 2 turns on and begins switching.
For slower start-up use a larger capacitor. For complete
shutdown tie RUN-SS2 to ground.
SW3 (Pin 6): Switch Node. The SW3 pin is the collector of
theinternalNPNbipolartransistorforswitchingregulator3.
Minimize trace area at this pin to keep EMI down.
E3 (Pin 7): This is switching regulator 3’s output and
the emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
VON (Pin 8): This is the delayed output for switching
regulator 3. VON reaches its programmed voltage after the
internal CT timer times out. Protection circuitry ensures
VON is disabled if any of the four outputs are more than
10% below normal voltage. This output is also disabled
when VON_CLK is high.
VONSINK(Pin9):Thisisanopen-collectoroutputcontrolled
by the VON_CLKpin.WhenVON_CLKislow,thispindrawsno
current and when VON_CLK is high, this pin draws current.
VON_CLK (Pin 10): This pin controls the output disconnect
device and the open collector of VONSINK. When this pin is
low, the VON pin is enabled and the VONSINK pin is a high
impedance. When this pin is high, the VON pin is disabled
and the VONSINK pin sinks current to ground.
PGOOD (Pin 11): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-channel
MOSFETtoprovideoutputdisconnectforAVDDasshownin
Figure 2. When switcher 2’s output reaches approximately
90% of its programmed voltage, PGOOD will be pulled to
ground. This will pull down on the gate of the MOSFET,
connecting AVDD. A 100k pull-up resistor between the
source and the gate of the P-channel MOSFET keeps it
off when switcher 2’s output is low.
VC3 (Pin 12): Control Voltage and Compensation Pin for
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 3.
CT (Pin 13): Timing Capacitor Pin. This is the input to
the VON timer and programs the time delay from all four
feedback pins reaching 1.125V to VON turning on. The CT
capacitor value can be set using the equation C = (20A
tDELAY)/1.1V.
GND (Pins 14, 17, 33): Ground.
SW2 (Pins 15, 16): Switch Node. The SW2 pin is the col-
lector of the internal NPN bipolar transistor for switching
regulator 2. Minimize trace area at this pin to keep EMI
down.
BIAS (Pins 18, 29): The BIAS pin is used to improve effi-
ciencywhenoperatingathigherinputvoltages.Connecting
this pin to the output of switching regulator 1 forces most
of the internal circuitry to draw its operating current from
VLOGIC rather than VIN. The drivers of switches 2, 3 and
4 and the LDO are supplied by BIAS. Switches 2, 3 and 4
and the LDO will not function until the BIAS pin reaches
approximately 2.7V. Both BIAS pins must be tied to VLOGIC.
FB2 (Pin 19): Feedback Pin. Tie the resistor divider tap
to this pin and set AVDD according to AVDD = 1.22V
(1 + R5/R6). Reference designators refer to Figure 2.
pin FuncTions
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