參數(shù)資料
型號: LT3500HMSE#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3.5 A SWITCHING REGULATOR, 2800 kHz SWITCHING FREQ-MAX, PDSO16
封裝: LEAD FREE, PLASTIC, MSOP-16
文件頁數(shù): 15/28頁
文件大?。?/td> 318K
代理商: LT3500HMSE#PBF
LT3500
22
3500fc
APPLICATIONS INFORMATION
To compensate the linear regulator, simply add a ceramic
capacitor from the LDRV pin to ground. Typical values
range from 0.01μF to 1μF. Figure 9 illustrates the transient
response with a 0.47μF output capacitor.
Linear Controller
By adding an external follower (NPN or NMOS), the LFB
and LDRV pins can be congured as a controller (Fig-
ure 10) for a low dropout regulator with increased output
capability.
The output current capability of Figure 10’s circuit is a
product of the LDRV current limit and beta of the external
NPN which is normally less than the current capability of
the LT3500. The dropout voltage for the circuit is set by the
saturation voltage of the external NPN, which is typically
300mV. The minimum VIN for the circuit to function prop-
erly is 2V plus the base emitter drop of the external NPN.
Replacing the NPN in Figure 10 with a NMOS transistor
can reduce the dropout voltage down to the RDS(ON) of the
Figure 9. Linear Regulator Transient Response
20μs/DIV
3500 F09
VOUT2
AC COUPLED
20mV/DIV
LOAD STEP
2.5mA TO 7.5mA
5mA/DIV
NMOS times the output current of the regulator. This also
increases the overall efciency of the system. However,
the minimum VIN increases to 2V plus the VGS at full load
of the transistor. Additionally, due to a lack of beta current
limiting, a shorted output can cause the switcher output
of the LT3500 to collapse.
Since the collector of the LDRV npn is connected internally
to VIN, you must consider the impact of LDRV current on
efciency and die temperature when conguring the linear
regulator/controller. For example, with VIN = 25V, LDRV =
3.3V and ILDRV = 10mA, power dissipation on the die will
be 217mW. For a typical 3.3V/1A switcher application,
this represents an additional 7% efciency loss and ap-
proximately 10 degrees rise in die temperature.
If the linear output of the LT3500 is not used, the LDRV
pin should be shorted to the LFB Pin.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 11
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents ow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
one location, ideally at the ground terminal of the output
Figure 10. Linear Controller
L1
3.3μH
C5
0.47μF
C7
22μF
C6
22μF
R1
27.4k
R2
8.06k
C1
2.2μF
C2
0.47μF
4.5V TO 36V
R6
40.2k
R5
49.9k
C3
220pF
3500 F10
VOUT1
3.5V
VOUT2
3.3V
1A
D2
BAT54
D1
B240A
BST
VIN
SW
FB
SHDN
SS
LT3500
RT/SYNC
VC
LDRV
PG
LFB
PG
R4
8.06k
R3
24.9k
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