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參數(shù)資料
| 型號(hào)： | LT3495BEDDB#TRPBF |
| 廠(chǎng)商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 0.78 A SWITCHING REGULATOR, PDSO10 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | LT3495BEDDB#TRPBF |
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LT3495/LT3495B/
LT3495-1/LT3495B-1
10
3495b1b1fa
APPLICATIONS INFORMATION
Figure 2. Feedback Connection Using
the CAP Pin or the VOUT Pin
SW
CAP
VCC
SHDN
CTRL
VOUT
FB
GND
R1
LT3495
C1
C3
VOUT
SW
CAP
VCC
SHDN
CTRL
VOUT
FB
GND
R1
3495 F02
LT3495
C1
SW
CAP
VCC
SHDN
CTRL
VOUT
FB
GND
3495 F03
LT3495
C1
ILOAD
Figure 1. CTRL to FB Transfer Curve
Figure 3. Improved Efciency Connection
Setting Output Voltage and the Auxiliary Reference
Input
The LT3495 series is equipped with both an internal
1.235V reference and an auxiliary reference input. This
allows the user to select between using the built-in refer-
ence and supplying an external reference voltage. The
voltage at the CTRL pin can be adjusted while the chip is
operating to alter the output voltage for purposes such
as display dimming or contrast adjustment. To use the
internal 1.235V reference, the CTRL pin must be held
higher than 1.5V. When the CTRL pin is held between 0V
and 1.235V, the parts will regulate the output such that
the FB pin voltage is nearly equal to the CTRL pin voltage.
At CTRL voltages close to 1.235V, a soft transition occurs
between the CTRL pin and the internal reference. Figure 1
shows this behavior.
To set the maximum output voltage, select the values of
R1 according to the following equation:
R1
= 76
VOUT
1.235
–1 k
When CTRL is used to override the internal reference,
the output voltage can be lowered from the maximum
value down to nearly the input voltage level. If the volt-
age source driving the CTRL pin is located at a distance
to the LT3495, a small 0.1μF capacitor may be needed to
bypass the pin locally.
Choosing a Feedback Node
The single feedback resistor may be connected to the
VOUT pin or to the CAP pin (see Figure 2). Regulating the
VOUT pin eliminates the output offset resulting from the
voltage drop across the output disconnect PMOS. Regu-
lating the CAP pin does not compensate for the voltage
drop across the output disconnect, resulting in an output
voltage VOUT that is slightly lower than the voltage set by
the resistor divider. Under most conditions, it is advised
that the feedback resistor be tied to the VOUT pin.
Connecting the Load to the CAP Node
The efciency of the converter can be improved by con-
necting the load to the CAP pin instead of the VOUT pin.
The power loss in the PMOS disconnect circuit is then
made negligible. By connecting the feedback resistor to
the VOUT pin, no quiescent current will be consumed in the
feedback resistor string during shutdown since the PMOS
transistor will be open (see Figure 3). The disadvantage
of this method is that the CAP node cannot go to ground
during shutdown, but will be limited to around a diode
drop below VCC. Loads connected to the part should only
sink current. Never force external power supplies onto
the CAP or VOUT pins.
CTRL VOLTAGE (V)
0
FB
VOL
TAGE
(V)
1.5
1.2
0.6
0.9
0.3
0
0.9
3495 F01
1.5
0.6
0.3
1.2
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