參數(shù)資料
型號(hào): LT3430IFE-1
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 6.5 A SWITCHING REGULATOR, 120 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 4.40 MM, PLASTIC, TSSOP-16
文件頁數(shù): 27/28頁
文件大?。?/td> 321K
代理商: LT3430IFE-1
LT3430/LT3430-1
8
34301fa
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT3430/LT3430-1 is used to
set output voltage and provide several overload protection
features. The rst part of this section deals with selecting
resistors to set output voltage and the second part talks
about foldback frequency and current limiting created by
the FB pin. Please read both parts before committing to
a nal design.
The suggested value for the LT3430 output divider resistor
(see Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. For the LT3430-1, choose
the resistors so that the Thevinin resistance of the divider
at the feedback pin is 7.5kΩ. The output voltage error
caused by ignoring the input bias current on the FB pin
is less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R
RVOUT
1
21 22
122
=
()
.
APPLICATIONS INFORMATION
average current through the diode and inductor is equal
to the short-circuit current limit of the switch (typically
4A for the LT3430/LT3430-1, folding back to less than
2A). Minimum switch on time limitations would prevent
the switcher from attaining a sufciently low duty cycle if
switching frequency were maintained at 200kHz (100kHz
LT3430-1), so frequency is reduced by about 5:1 (3:1
LT3430-1) when the feedback pin voltage drops below
0.8V (see Frequency Foldback graph). This does not affect
operation with normal load conditions; one simply sees
a gear shift in switching frequency during start-up as the
output voltage rises.
In addition to lower switching frequency, the LT3430/
LT3430-1 also operate at lower switch current limit when
the feedback pin voltage drops below 0.6V. Q2 in Figure 2
performs this function by clamping the VC pin to a voltage
less than its normal 2.1V upper clamp level. This foldback
current limit greatly reduces power dissipation in the IC,
diode and inductor during short-circuit conditions. External
synchronization is also disabled to prevent interference
with foldback operation. Again, it is nearly transparent to
the user under normal load conditions. The only loads that
may be affected are current source loads which maintain
full load current with output voltage less than 50% of
nal value. In these rare situations the feedback pin can
be clamped above 0.6V with an external diode to defeat
foldback current limit. Caution: clamping the feedback
pin means that frequency shifting will also be defeated,
so a combination of high input voltage and dead shorted
output may cause the LT3430/LT3430-1 to lose control
of current limit.
The internal circuitry which forces reduced switching
frequency also causes current to ow out of the feedback
pin when output voltage is low. The equivalent circuitry
is shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and LT3430 reduces frequency at the rate
of approximately 1.4kHz/A. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance (RTHEV) must be low
enough to pull 115A out of the FB pin with 0.44V on
the pin (RTHEV ≤ 3.8k)(LT3430-1 RTHEV ≈ 7.5k). The net
result is that reductions in frequency and current limit
are affected by output voltage divider impedance. Cau-
Table 1. *LT3430, **LT3430-1
OUTPUT
VOLTAGE
(V)
R2
(kΩ)
R1
(NEAREST 1%)
(kΩ)
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
3*
4.99
7.32
+0.32
3.3*
4.99
8.45
–0.43
5*
4.99
15.4
–0.30
12*
4.12
46.4
–0.27
3**
12.7
18.7
+0.54
3.3**
12.1
20.5
–0.40
5**
10
30.9
–0.20
12**
8.25
73.2
+0.37
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
and in the external diode and inductor during short-cir-
cuit conditions. A shorted output requires the switching
regulator to operate at very low duty cycles, and the
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