LTC3412A
14
3412afb
When a load step occurs, VOUT immediately shifts by an
amount equal to
ΔILOAD(ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3412A in an
application with the following specifications:
VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 3A,
IOUT(MIN) = 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
Rk
k
OSC
==
308 10
110
10
298
11
6
.
–
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
L
V
MHz
A
V
H
=
=μ
25
11 2
1
25
33
051
.
()( .
)
–
.
Using a 0.47
μH inductor results in a maximum ripple
current of:
Δ=
μ
=
I
V
MHz
H
V
A
L
25
10 47
1
25
33
129
.
()( .
)
–
.
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100
μF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
IA
V
A
RMS
=
=
()
.
–.
3
25
33
25
11 29
Decoupling the PVIN and SVIN pins with two 22μF capaci-
tors is adequate for most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.50V by the resistor
divider consisting of R2 and R3. According to the graph of
Minimum Peak Inductor Current vs Burst Clamp Voltage
in the Typical Performance Characteristics section, a burst
clamp voltage of 0.5V will set the minimum inductor
current, IBURST, to approximately 1.1A.
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
RR
k
R
V
2
3
185
1
2
3
08
050
+=
.
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
1
185
25
08
1 392
+=
=
R
k
V
Rk
.
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412A. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412A.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
APPLICATIO S I FOR ATIO
WU
UU