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| 型號： | LT1990IS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF +/-250V MCRPWR 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.55 V/µs |
| -3db帶寬： | 105kHz |
| 電壓 - 輸入偏移： | 900µV |
| 電流 - 電源： | 140µA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 36 V，±1.35 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
LT1990
14
1990fb
VCM+ ≤ 27 V+ – 26 VREF – 23 – VGAIN
VCM– ≥ 27 V– – 26 VREF + 27 – VGAIN
For split supplies over about
±11V,thefull±250Vcommon
mode range is normally available (with VREF a small
fraction of the supply). With lower supply voltages, an
appropriate selection of VREF can tailor the input common
mode range to a specific requirement. As an example, the
following low supply voltage scenarios are readily imple-
mented with the LT1990:
Supply
VREF
VCM Range
+3V
1.25V
–5V to 25V (e.g. 12V automotive environment)
+5V
1.25V
–5V to 80V (e.g. 42V automotive environment)
+5V
4.00V
–77V to 8V (e.g. telecom environment;
use downward signaling)
Configuring Other Gains
An intermediate gain G ranging between 1 and 10 may be
produced by placing an adjustable resistance between the
GAIN1 and GAIN2 pins according to the following nominal
relationship:
RGAIN ≈ (180k/(G – 1)) – 20k
While the expression is exact, the value is approximate
because the absolute resistance of the internal network
could vary on a unit-to-unit basis by as much as
±30%
from the nominal figures and the external gain resistance
is required to accommodate that deviation. Once ad-
justed, however, the gain stability is excellent by virtue of
the –30ppm/
°C typical temperature coefficient offered by
the on-chip thin-film resistor process.
Preserving and Enhancing Common Mode Rejection
The basic difference amplifier topology of the LT1990
requires that source impedances seen by the input pins
+IN and –IN, should be matched to within a few tens of
ohms to avoid increasing common mode induced errors
beyond the basic production limits of the part. Known
source imbalances beyond that level should be compen-
sated for by the addition of series resistance to the lower-
impedance source. Also the source impedance of a signal
connected to the REF pin must be on the order of a few
ohms or less to preserve the high accuracy of the LT1990.
APPLICATIO S I FOR ATIO
WU
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Primary Features
The LT1990 is a complete gain-block solution for high
input common mode voltage applications, incorporating a
low power precision operational amplifier providing rail-
to-rail output swing along with on-chip precision thin-film
resistors for high accuracy. The Block Diagram shows the
internal architecture of the part. The on-chip resistors
form a modified difference amplifier including a reference
port for introducing offset or other additive waveforms.
With pin-strapping alone either unity gain or gain of 10 is
produced with high precision. The resistor network is
designed to produce internal common-mode voltage divi-
sion of 27 so that a very large input range is available
compared to the power supply voltage(s) used by the
LT1990 itself. The LT1990 is ideally suited to situations
where relatively small signals need to be extracted from
high voltage circuits, as is the case in many current
monitoring instrumentation applications for example. With
the ability to accept a range of input voltages well outside
the limits of the local power rails and its greater than 1M
input impedances, development of precision low power
over-the-top and under-the-bottom instrumentation de-
signs is greatly simplified with the LT1990 single chip
solution over conventional discrete implementations.
Classic Difference Amplifier
Used in the basic difference amplifier topology where the
gain G is pin-strap configurable to be unity or ten, the
following relationship is realized:
VO = G (V+IN – V–IN) + VREF
To operate in unity gain, the GAIN1 and GAIN2 pins are left
disconnected. For G = 10 operation, the GAIN1 and GAIN2
pins are simply connected to the REF pin.
The input common mode range capability is up to
±250V,
governed by the following relationships:
For G = 1 and G = 10 where GAIN1 and GAIN2 are only tied
together (not grounded,etc):
VCM+ ≤ 27 V+ – 26 VREF – 23
VCM– ≥ 27 V– – 26 VREF + 27
For G = 10 where GAIN1 and GAIN2 are tied to a common
potential VGAIN:
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