參數(shù)資料
型號: LT1970
廠商: Linear Technology Corporation
英文描述: 500mA Power Op Amp with Adjustable Precision Current Limit
中文描述: 500mA的電源運算放大器精密可調電流限制
文件頁數(shù): 8/12頁
文件大?。?/td> 233K
代理商: LT1970
8
LT1970
1970f
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISRC may be left open if
this function is not monitored.
ISNK (Pin 17):
Sinking Current Limit Digital Output Flag.
ISNK is an open collector digital output. ISNK pulls low
whenever the sinking current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISNK may be left open if
this function is not monitored.
TSD (Pin 18):
Thermal Shutdown Digital Output Flag. TSD
is an open collector digital output. TSD pulls low whenever
the internal thermal shutdown circuit activates, typically at
a die temperature of 160
°
C. This pin can sink up to 10mA
of output current. The TSD flag is off when the die
temperature is within normal operating temperatures.
ISRC, ISNK and TSD may be wired “OR” together if
desired. ISNK may be left open if this function is not
monitored. Thermal shutdown activation should prompt
the user to evaluate electrical loading or thermal environ-
mental conditions.
V
+
(Pin 19):
Output Stage Positive Supply. V
+
may equal
V
CC
or may be smaller in magnitude. Only output stage
current flows through V
+
, all other current flows into V
CC
.
V
+
may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels
above the rated 500mA of the on-chip output devices.
Unless used to drive boost transistors, V
+
should be
decoupled to ground with a low ESR capacitor.
Package Base:
The exposed backside of the package is
electrically connected to the V
EE
pins on the IC die. The
package base should be soldered to a heat spreading pad
on the PC board that is electrically connected to V
EE
.
PIU
VC
SNK
(Pin 12):
Sink Current Limit Control Voltage Input.
The current sink limit amplifier will activate when the
sense voltage between SENSE
+
and SENSE
equals
–1.0 V
VCSNK
/10. VC
SNK
may be set between V
COMMON
and V
COMMON
+ 6V. The transfer function between VC
SNK
and V
SENSE
is linear except for very small input voltages at
VC
SNK
< 60mV. V
SENSE
limits at a minimum set point of
4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
VC
SRC
(Pin 13):
Source Current Limit Control Voltage
Input. The current source limit amplifier will activate
when the sense voltage between
SENSE
+
and
SENSE
equals V
VCSRC
/10. VC
SRC
may be set between V
COMMON
and V
COMMON
+ 6V. The transfer function between VC
SRC
and V
SENSE
is linear except for very small input voltages
at VC
SRC
< 60mV. V
SENSE
limits at a minimum set point
of 4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously.
To force
zero output current, the ENABLE pin can be taken low.
COMMON (Pin 14):
Control and ENABLE inputs and flag
outputs are referenced to the COMMON pin. COMMON
may be at any potential between V
EE
and V
CC
– 3V. In
typical applications, COMMON is connected to ground.
ENABLE (Pin 15):
ENABLE Digital Input Control. When
taken low this TTL-level digital input turns off the amplifier
output and drops supply current to less than 1mA. Use the
ENABLE pin to force zero output current. Setting VC
SNK
=
VC
SRC
= 0V allows I
OUT
=
±
4mV/R
SENSE
to flow in or out
of V
OUT
.
ISRC (Pin 16):
Sourcing Current Limit Digital Output Flag.
ISRC is an open collector digital output. ISRC pulls low
whenever the sourcing current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
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