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| 型號： | LT1884AIN8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP DUAL R-R PICO/IN 8DIP |
| 標準包裝： | 50 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 1 V/µs |
| 增益帶寬積： | 2.2MHz |
| 電流 - 輸入偏壓： | 150pA |
| 電壓 - 輸入偏移： | 25µV |
| 電流 - 電源： | 850µA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 36 V，±1.35 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
LT1884/LT1885
9
The LT1884/LT1885 dual op amp features exceptional
input precision with rail-to-rail output swing. Slew rate
and small-signal bandwidth are superior to other amplifi-
ers with comparable input precision. These characteris-
tics make the LT1884/LT1885 a convenient choice for
precision low voltage systems and for improved AC per-
formance in higher voltage precision systems. Maintain-
ing the advantage of the precision inherent in the amplifier
depends upon proper applications circuit design and
board layout.
Preserving Input Precision
Preserving the input voltage accuracy of the LT1884/
LT1885 requires that the applications circuit and PC board
layout do not introduce errors comparable to or greater
than the 30
V offset. Temperature differentials across the
input connections can generate thermocouple voltages of
10s of microvolts. PC board layouts should keep connec-
tions to the amplifier’s input pins close together and away
from heat dissipating components. Air currents across the
board can also generate temperature differentials.
The extremely low input bias currents, 100pA, allow high
accuracy to be maintained with high impedance sources
and feedback networks. The LT1884/LT1885’s low input
bias currents are obtained by using a cancellation circuit
on-chip. This causes the resulting IBIAS+ and IBIAS– to be
uncorrelated, as implied by the IOS specification being
comparable to the IBIAS. The user should not try to balance
the input resistances in each input lead, as is commonly
recommended with most amplifiers. The impedance at
either input should be kept as small as possible to mini-
mize total circuit error.
PC board layout is important to ensure that leakage
currents do not corrupt the low IBIAS of the amplifier. In
high precision, high impedance circuits, the input pins
should be surrounded by a guard ring of PC board
interconnect, with the guard driven to the same common
mode voltage as the amplifier inputs.
Input Common Mode Range
The LT1884/LT1885 output is able to swing close to each
power supply rail, but the input stage is limited to operat-
ing between VEE + 0.8V and VCC – 0.9V. Exceeding this
common mode range will cause the gain to drop to zero;
however, no gain reversal will occur.
Input Protection
The inverting and noninverting input pins of the LT1884/
LT1885 have limited on-chip protection. ESD protection is
provided to prevent damage during handling. The input
transistors have voltage clamping and limiting resistors to
protect against input differentials up to 10V. Short tran-
sients above this level will also be tolerated. If the input
pins may be subject to a sustained differential voltage
above 10V, external limiting resistors should be used to
prevent damage to the amplifier. A 1k resistor in each input
lead will provide protection against a 30V differential
voltage.
Capacitive Loads
The LT1884/LT1885 can drive capacitive loads up to
300pF when configured for unity gain. The capacitive load
driving capability increases as the amplifier is used in
higher gain configurations. Capacitive load driving may
also be increased by decoupling the capacitance from the
output with a small resistance.
Input Bias Currents
While it may be tempting to seek out a JFET amplifier for
low input bias current, remember that bipolar devices
improve with temperature while JFETs degrade.
APPLICATIO S I FOR ATIO
WU
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