參數(shù)資料
型號(hào): LT1812CS6
元件分類: 運(yùn)算放大器
英文描述: Operational Amplifier
中文描述: 運(yùn)算放大器
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 246K
代理商: LT1812CS6
LT1813
APPLICATIO
S I
N
FOR
ATIO
U
Layout and Passive Components
The LT1813 amplifier is more tolerant of less than ideal
layouts than other high speed amplifiers. For maximum
performance (for example, fast settling) use a ground
plane, short lead lengths and RF-quality bypass capacitors
(0.01
μ
F to 0.1
μ
F). For high drive current applications, use
low ESR bypass capacitors (1
μ
F to 10
μ
F tantalum).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole that can cause peaking or
oscillations. If feedback resistors greater than 2k are used,
a parallel capacitor of value
C
F
> R
G
C
IN
/R
F
should be used to cancel the input pole and optimize
dynamic performance. For applications where the DC
noise gain is 1 and a large feedback resistor is used, C
F
should be greater than or equal to C
IN
. An example would
be an I-to-V converter.
W
U
Input Considerations
Each of the LT1813 amplifier inputs is the base of an NPN
and PNP transistor whose base currents are of opposite
polarity and provide first-order bias current cancellation.
Because of variation in the matching of NPN and PNP beta,
the polarity of the input current can be positive or negative.
The offset current does not depend on beta matching and
is well controlled. The use of balanced source resistance
at each input is recommended for applications where DC
accuracy must be maximized. The inputs can withstand
differential input voltages of up to 3V without damage and
need no clamping or source resistance for protection.
Differential inputs generate the large supply currents (up
to 40mA) required for high slew rates. Typically, power
dissipation does not significantly increase in normal,
closed-loop operation because of the low duty cycle of the
transient inputs.
The device should not be used as a comparator
because
with sustained differential inputs, excessive power dissi-
pation may result.
Capacitive Loading
The LT1813 is stable with a 1000pF capacitive load which
is outstanding for a 100MHz amplifier. This is accom-
plished by sensing the load induced output pole and
adding compensation at the amplifier gain node. As the
capacitive load increases, both the bandwidth and phase
margin decrease so there will be peaking in the frequency
domain and in the transient response. Coaxial cable can be
driven directly, but for best pulse fidelity, a resistor of
value equal to the characteristic impedance of the cable
(i.e., 75
) should be placed in series with the output. The
other end of the cable should be terminated with the same
value resistor to ground.
Slew Rate
The slew rate is proportional to the differential input
voltage. Highest slew rates are therefore seen in the
lowest gain configurations. For example, a 5V output step
in a gain of 10 has a 0.5V input step, whereas in unity gain
there is a 5V input step. The LT1813 is tested for slew rate
in a gain of –1. Lower slew rates occur in higher gain
configurations.
Power Dissipation
The LT1813 combines high speed and large output drive
in a small package. It is possible to exceed the maximum
junction temperature under certain conditions. Maximum
junction temperature (T
J
) is calculated from the ambient
temperature (T
A
) and power dissipation (P
D
) as follows:
LT1813CS8: T
J
= T
A
+ (P
D
150
°
C/W)
Power dissipation is composed of two parts. The first is
due to the quiescent supply current and the second is
due to on-chip dissipation caused by the load current.
The worst-case load induced power occurs when the
output voltage is at 1/2 of either supply voltage (or the
maximum swing if less than 1/2 supply voltage). For each
amplifier:
P
DMAX
= (V
+
– V
)(I
SMAX
) + (V
+
/2)
2
/R
L
or
P
DMAX
= (V
+
– V
)(I
SMAX
) + (V
+
– V
OMAX
)(V
OMAX
/R
L
)
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