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參數(shù)資料
| 型號： | LT1805 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Single/Dual/Quad 60MHz, 20V/us, Low Power, Rail-to-Rail Input and Output Precision Op Amps |
| 中文描述： | 單/雙/四路60MHz時(shí)，20V/us，低功耗，軌至軌輸入和輸出精密運(yùn)算放大器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 279K |
| 代理商： | LT1805 |
LT6220/LT6221/LT6222
8
sn622012 622012fs
SYMBOL
V
OS
PARAMETER
Input Offset Voltage
CONDITIONS
V
CM
= –5V
V
CM
= –5V (DD Package)
V
CM
= –5V (S5 Package)
V
CM
= 5V
V
CM
= 5V (S5 Package)
V
CM
= – 5V
to 3.5V
MIN
TYP
150
300
350
0.75
1
90
175
300
1.5
3.5
25
300
15
20
20
20
70
8
100
100
MAX
800
1300
2000
3.5
4.5
950
1350
2200
7.5
15
200
900
250
350
150
150
UNITS
●
●
●
●
●
μ
V
μ
V
μ
V
mV
mV
μ
V
μ
V
μ
V
V
OS
Input Offset Voltage Shift
Input Offset Voltage Match (Channel-to-Channel) V
CM
= –5V
(Note 9)
Input Offset Voltage Drift (Note 8)
●
●
●
V
CM
= –5V (DD Package)
V
OS
TC
●
●
μ
V/
°
C
μ
V/
°
C
(S5 Package)
V
CM
= –4V
V
CM
= 4.8V
V
CM
= –4V
V
CM
= 4.8V
V
CM
= –4V
V
CM
= 4.8V
V
O
= –4V to 4V, R
L
= 1k
V
O
= –1V to 1V, R
L
= 100
V
CM
= –5V to 3.5V
I
B
Input Bias Current
●
●
nA
nA
nA
nA
nA
nA
Input Bias Current Match (Channel-to-Channel)
(Note 9)
Input Offset Current
●
●
I
OS
●
●
A
VOL
Large Signal Voltage Gain
●
●
25
2.5
79
74
–5
79
74
V/mV
V/mV
CMRR
Common Mode Rejection Ratio
CMRR Match (Channel-to-Channel) (Note 9)
Input Common Mode Range
Power Supply Rejection Ratio
PSRR Match (Channel-to-Channel) (Note 9)
Output Voltage Swing LOW (Note 7)
●
dB
dB
V
dB
dB
mV
mV
mV
mV
mV
mV
mA
mA
MHz
V/
μ
s
●
●
5
PSRR
V
S+
= 2.5V to 10V, V
S–
= 0V, V
CM
= 0V
●
104
104
10
120
220
10
160
325
30
1.4
50
15
●
V
OL
No Load
I
SINK
= 5mA
I
SINK
= 10mA
No Load
I
SOURCE
= 5mA
I
SOURCE
= 10mA
●
●
●
60
240
450
60
325
650
V
OH
Output Voltage Swing HIGH (Note 7)
●
●
●
I
SC
I
S
GBW
SR
Short-Circuit Current
Supply Current
Gain-Bandwidth Product
Slew Rate
●
12.5
●
2.25
Frequency = 1MHz
A
V
= –1, R
L
= 1k,
V
O
=
±
4V,
Measure at V
O
=
±
2V
●
●
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
The inputs are protected by back-to-back diodes. If the differential
input voltage exceeds 1.4V, the input current should be limited to less than
10mA.
Note 3:
A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4:
The LT6220C/LT6221C/LT6222C and LT6220I/LT6221I/LT6222I
are guaranteed functional over the temperature range of –40
°
C and 85
°
C.
Note 5:
The LT6220C/LT6221C/LT6222C are guaranteed to meet specified
performance from 0
°
C to 70
°
C. The LT6220C/LT6221C/LT6222C are
designed, characterized and expected to meet specified performance from
–40
°
C to 85
°
C but is not tested or QA sampled at these temperatures. The
LT6220I/LT6221I/LT6222I are guaranteed to meet specified performance
from –40
°
C to 85
°
C.
Note 6:
Minimum supply voltage is guaranteed by power supply rejection
ratio test.
Note 7:
Output voltage swings are measured between the output and
power supply rails.
Note 8:
This parameter is not 100% tested.
Note 9:
Matching parameters are the difference between amplifiers A and
D and between B and C on the LT6222; between the two amplifiers on the
LT6221.
Note 10:
Thermal resistance (
θ
JA
) varies with the amount of PC board
metal connected to the package. The specified values are for short traces
connected to the leads. If desired, the thermal resistance can be
substantially reduced by connecting Pin 2 of the LT6220CS5/LT6220IS5 or
the underside metal of DD packages to a larger metal area (V
S–
trace).
ELECTRICAL CHARACTERISTICS
temperature range. V
S
=
±
5V, V
CM
= 0V, V
OUT
= 0V, unless otherwise noted. (Note 5)
The
●
denotes the specifications which apply over the –40
°
C
≤
T
A
≤
85
°
C
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