參數(shù)資料
型號(hào)： LT1776I
廠(chǎng)商： Linear Technology Corporation
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述： 抗輻射高效，5安培開(kāi)關(guān)穩(wěn)壓器
文件頁(yè)數(shù)： 12/20頁(yè)
文件大小： 147K
代理商： LT1776I
12
LT1776
APPLICATIO
S I
FOR
ATIO
U
W
U
U
P
AC
= 1/2 V
IN
I
OUT
(t
r
+ t
f
+ 30ns) f
t
r
= (V
IN
/1.6)ns in high dV/dt mode
(V
IN
/0.16)ns in low dV/dt mode
t
f
= (V
IN
/1.6)ns (irrespective of dV/dt mode)
f = switching frequency
Total power dissipation of the die is simply the sum of
quiescent, DC and AC losses previously calculated.
P
D(TOTAL)
= P
Q
+ P
DC
+ P
AC
Frequency Compensation
Loop frequency compensation is performed by connect-
ing a capacitor, or in most cases a series RC, from the
output of the error amplifier (V
C
pin) to ground. Proper
loop compensation may be obtained by empirical meth-
ods as described in detail in Application Note 19. Briefly,
this involves applying a load transient and observing the
dynamic response over the expected range of V
IN
and
I
LOAD
values.
As a practical matter, a second small capacitor, directly
from the V
C
pin to ground is generally recommended to
attenuate capacitive coupling from the V
SW
pin. A typical
value for this capacitor is 100pF. (See Switch Node Con-
siderations).
Switch Node Considerations
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power path. B field (magnetic) radiation is minimized by
keeping output diode, switch pin and input bypass capaci-
tor leads as short as possible. E field radiation is kept low
by minimizing the length and area of all traces connected
to the switch pin (V
SW
). A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
However, remember that oscillator slowdown to achieve
short-circuit protection (discussed above) is dependent
on FB pin behavior, and this in turn, is sensitive to FB node
external impedance. Figure 2 shows the typical relation-
ship between FB divider Thevenin voltage and impedance,
and oscillator frequency. This shows that as feedback
network impedance increases beyond 10k, complete os-
cillator slowdown is not achieved, and short-circuit pro-
tection may be compromised. And as a practical matter,
the product of FB pin bias current and larger FB network
impedances will cause increasing output voltage error.
(Nominal cancellation for 10k of FB Thevenin impedance
is included internally.)
Thermal Considerations
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110
°
C/W
for the 8-pin SO (S8) and 130
°
C/W for 8-pin PDIP (N8).
Quiescent power is given by:
P
Q
= I
IN
V
IN
+ I
VCC
V
OUT
(This assumes that the V
CC
pin is connected to V
OUT
.)
Power loss internal to the LT1776 related to actual output
current is composed of both DC and AC switching losses.
These can be roughly estimated as follows:
DC switching losses are dominated by output switch “ON
voltage”, i.e.,
P
DC
= V
ON
I
OUT
DC
V
ON
= Output switch ON voltage, typically 1V at 500mA
I
OUT
= Output current
DC = ON duty cycle
AC switching losses are typically dominated by power lost
due to the finite rise time and fall time at the V
SW
node.
Assuming, for simplicity, a linear ramp up of both voltage
and current and a current rise/fall time equal to 15ns,
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