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參數(shù)資料
| 型號(hào)： | LT1767EMS8#TR-1.8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 232K |
| 代理商： | LT1767EMS8#TR-1.8 |
13
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
WU
U
Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:
P
W
PW
SW
BOOST
Q
= (
)( )()
+
()()( )()
=+
=
= ()(
)
=
()=
027 1
5
10
17 10
1 10 1 25 10
0 135 0 21 0 34
51 50
10
005
10 0 001
0 01
2
96
2
.
..
.
/
.
..
Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W.
Thermal resistance for LT1767 package is influenced by
the presence of internal or backside planes. With a full
plane under the package, thermal resistance will be about
110
°C/W. No plane will increase resistance to about
150
°C/W. To calculate die temperature, use the appropri-
ate thermal resistance number and add in worst-case
ambient temperature:
TJ = TA + θJA (PTOT)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
P
VV
V
I
V
DIODE
F
IN
OUT
LOAD
IN
= ()
()(
)
VF = Forward voltage of diode (assume 0.5V at 1A)
PW
DIODE =
()
()( )
=
05 12 5 1
12
029
.
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower VF diode can improve efficiency by several percent.
PINDUCTOR = (ILOAD) (LDCR)
LDCR = Inductor DC resistance (assume 0.1)
PINDUCTOR = (1) (0.1) = 0.1W
Typical thermal resistance of the board is 35
°C/W. At an
ambient temperature of 65
°C,
Tj = 65 + 110 (0.4) + 35 (0.39) = 123°C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations. If a true die temperature is required, a mea-
surement of the SYNC to GND pin resistance can be used.
The SYNC pin resistance across temperature must first be
calibrated, with no device power, in an oven. The same
measurement can then be used in operation to indicate the
die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered – the
worse the board layout, the more difficult the circuit will be
to stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section
first. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the VC compensation
to a ground track carrying significant switch current. In
addition, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT1767 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 7,
with both tantalum and ceramic capacitor equivalent cir-
cuits. The LT1767 can be considered as two gm blocks, the
error amplifier and the power stage.
Figure 8 shows the overall loop response with a 330pF VC
capacitor and a typical 100
F tantalum output capacitor.
The response is set by the following terms:
Error amplifier:
DC gain set by gm and RL = 850 500k = 425.
Pole set by CF and RL = (2π 500k 330p)–1 = 965Hz.
Unity-gain set by CF and gm = (2π 330p 850–1)–1 =
410kHz.
Power stage:
DC gain set by gm and RL (assume 10) = 2.5 10 = 25.
Pole set by COUT and RL = (2π 100 10)–1 = 159Hz.
Unity-gain set by COUT and gm = (2π 100 2.5–1)–1 =
3.98kHz.
Tantalum output capacitor:
Zero set by COUT and CESR = (2π 100 0.1)–1 = 15.9kHz.
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