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參數(shù)資料
| 型號(hào)： | LT1724IS#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC OPAMP 200MHZ QUAD 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 70 V/µs |
| 增益帶寬積： | 200MHz |
| 電流 - 輸入偏壓： | 40nA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 3.7mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 10 V，±2.5 V ~ 5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SO |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | LT1724ISTR |
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LT1722/LT1723/LT1724
13
172234fb
The LT1722/LT1723/LT1724 may be inserted directly into
many operational amplier applications improving both DC
and AC performance, as well as noise and distortion.
Layout and Passive Components
The LT1722/LT1723/LT1724 ampliers are more tolerant
of less than ideal layouts than other high speed ampliers.
For maximum performance (for example, fast settling time)
use a ground plane, short lead lengths and RF quality
bypass capacitors (0.01μF to 0.1μF). For high drive current
applications, use low ESR supply bypass capacitors (1μF
to 10μF tantalum). The output/input parasitic coupling
should be minimized when high frequency performance
is required.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole that can cause peaking
or even oscillations. In parallel with the feedback resistor,
a capacitor of value:
CF > RG CIN/RF
should be used to cancel the input pole and optimize
dynamic performance. For unity-gain applications where
a feedback resistor is used, such as an I-to-V converter,
CF should be ve times greater than CIN; an optimum
value for CF is 10pF.
Input Considerations
Each of the LT1722/LT1723/LT1724 inputs is protected with
back-to-back diodes across the bases of the NPN input
devices. If greater than 0.7V differential input voltages are
anticipated, the input current must be limited to less than
10mA with an external series resistor. Each input also has
two ESD clamp diodes—one to each supply. If an input is
driven beyond the supply, limit the current with an external
resistor to less than 10mA. The input stage protection
circuit is shown in Figure 1.
The input currents of the LT1722/LT1723/LT1724 are
typically in the tens of nA range due to the bias current
cancellation technique used at the input. As the input
offset current can be greater than either input current,
APPLICATIONS INFORMATION
Figure 1. Input Stage Protection
adding resistance to balance source resistance is not
recommended. The value of the source resistor should
be below 12k as it actually degrades DC accuracy and
also increases noise.
Total Input Noise
The total input noise of the LT1722/LT1723/LT1724 is
optimized for a source resistance between 0.8k and 12k.
Within this range, the total input noise is dominated by
the noise of the source resistance itself. When the source
resistance is below 0.8k, voltage noise of the amplier
dominates. When the source resistance is above 12k, the
input noise current is the dominant contributor.
Capacitive Loading
The LT1722/LT1723/LT1724 drive capacitive loads up to
100pF with unity gain. As the capacitive load increases,
both the bandwidth and the phase margin decrease causing
peaking in the frequency response and overshoot in the
transient response. When there is a need to drive a larger
capacitive load, a 25Ω series resistance assures stability
with any value of load capacitor. A feedback capacitor also
helps to reduce any peaking.
Power Dissipation
The LT1722/LT1723/LT1724 combine high speed and
large output drive in a small package. Maximum junction
temperature(TJ)iscalculatedfromtheambienttemperature
(TA), power dissipation per amplier (PD) and number of
ampliers (n) as follows:
TJ = TA + (n PD θJA)
D1
D3
+IN
D4
D5
D6
1723 F01
D2
I1
I2
R
Q1
REXT
Q2
VS
+
VS
–
–IN
REXT
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