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| 型號： | LT1721IS#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP R-RINOUT QUAD 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | UltraFast™ |
| 類型： | 通用 |
| 元件數(shù)： | 4 |
| 輸出類型： | CMOS，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 3mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 6µA @ 5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 7mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 10ns |
| 磁滯： | 7mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
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LT1720/LT1721
19
17201fc
Optional Logarithmic Pulse Stretcher
The fourth comparator of the quad LT1721 can be put to
work as a logarithmic pulse stretcher. This simple circuit
can help tremendously if you don’t have a fast enough
oscilloscope (or control circuit) to easily capture 3ns
pulse widths (or faster). When an input pulse occurs, C2
is charged up with a 180ns capture2 time constant. The
hysteresis and 10mV offset across R3 are overcome within
the rst nanosecond3, switching the comparator output
high. When the input pulse subsides, C2 discharges with
a 540ns time constant, keeping the comparator on until
the decay overrides the 10mV offset across R3 minus
hysteresis. Because of this exponential decay, the output
pulse width will be proportional to the logarithm of the
input pulse width. It is important to bypass the circuit’s
VCC well to avoid coupling into the resistive divider. R4
keeps the quiescent input voltage in a range where forward
leakage of the diode due to the 0.4V VOL of the driving
comparator is not a problem.
Neglecting some effects4, the output pulse is related to
the input pulse as:
tOUT = τ2 ln {VCH [1 – exp (–tP/τ1)]/(VOFF – VH/2)}
–
τ1 ln [VCH/(VCH – VOFF – VH/2)]
+ tP
(1)
where
tP = input pulse width
tOUT = output pulse width
τ1 = R1 || R2 C2
the capture time constant
τ2 = R2 C2
the decay time constant
VOFF = 10mV
the voltage drop across R1
VH = 3.5mV
LT1721 hysteresis
VC = VIN – VFDIODE
the input pulse voltage after
the diode drop
VCH = VC R2/(R1 + R2)
the effective source voltage
for the charge
APPLICATIONS INFORMATION
For simplicity, with tP < τ1, and neglecting the very slight
delay in turn-on due to offset and hysteresis, the equation
can be approximated by:
tOUT = τ2 ln [(VCH tP/τ1)/(VOFF – VH/2)]
(2)
For example, an 8ns input pulse gives a 1.67μs output
pulse. Doubling the input pulse to 16ns lengthens the
output pulse by 0.37μs. Doubling the input pulse again
to 32ns adds another 0.37μs to the output pulse, and so
on. The rate of 0.37μs per octave falls out of the above
equation as:
ΔtOUT/octave = τ2 ln(2)
(3)
There is
±0.01μs jitter5 in the output pulse which gives an
uncertainty referred to the input pulse of less than 2% (60ps
resolution on a 3ns pulse with a 60MHz oscilloscope—not
bad!). The beauty of this circuit is that it gives resolution
precisely where it’s hardest to get. The jitter is due to a
combination of the slow decay of the last few millivolts
on C2 and the 4nV/√Hz noise and 400MHz bandwidth of
the LT1721 input stage. Increasing the offset across R3
or decreasing
τ2 will decrease this jitter at the expense of
dynamic range.
The circuit topology itself is extremely fast, limited theo-
retically only by the speed of the diode, the capture time
constant
τ1 and the pulse source impedance. Figure 14
shows results achieved with the implementation shown,
compared to a plot of Equation (1). The low end is limited
by the delivery time of the upstream comparators. As the
input pulse width is increased, the log function is con-
strained by the asymptotic RC response but, rather than
becoming clamped, becomes time linear. Thus, for very
long input pulses the third term of Equation (1) dominates
and the circuit becomes a 3μs pulse stretcher.
2 So called because the very fast input pulse is “captured,” for later examination, as a charge on
the capacitor.
3 Assuming the input pulse slew rate at the diode is innite. This effective delay constant, about
0.4% of
τ1 or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited
LT1721, this effective delay will be 2ns.
4 VCisdependentontheLT1721outputvoltageandnonlineardiodecharacteristics.Also,theThevenin
equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above ground.
5 Output jitter increases with inputs pulse widths below ~3ns.
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