參數(shù)資料
型號(hào): LT1719CS8#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 4/22頁(yè)
文件大?。?/td> 0K
描述: IC COMP R-R I/O SGL 3/5V 8-SOIC
標(biāo)準(zhǔn)包裝: 100
系列: UltraFast™
類型: 通用
元件數(shù): 1
輸出類型: CMOS,滿擺幅,TTL
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
電壓 - 輸入偏移(最小值): 2.5mV @ ±5V
電流 - 輸入偏壓(最小值): 6µA @ ±5V
電流 - 輸出(標(biāo)準(zhǔn)): 20mA
電流 - 靜態(tài)(最大值): 9mA
CMRR, PSRR(標(biāo)準(zhǔn)): 70dB CMRR,80dB PSRR
傳輸延遲(最大): 4.2ns
磁滯: 7mV
工作溫度: 0°C ~ 70°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1323 (CN2011-ZH PDF)
LT1719
12
1719fa
on the common mode and power supply dependence of
the hysteresis voltage.
Additional hysteresis may be added externally. The rail-
to-rail outputs of the LT1719 make this more predictable
than with TTL output comparators due to the LT1719’s
small variability of VOH (output high voltage).
To add additional hysteresis, set up positive feedback
by adding additional external resistor R3 as shown in
Figure 4. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1719 pulls the
outputs to + VS and ground to within 200mV of the rails
with light loads, and to within 400mV with heavy loads.
For the load of most circuits, a good model for the voltage
on the right side of R3 is 300mV or +VS – 300mV, for a
total voltage swing of (+VS – 300mV) – (300mV) = +VS
– 600mV.
The exact amount of hysteresis will vary from part to part
as indicated in the specications table. The hysteresis level
will also vary slightly with changes in supply voltage and
common mode voltage. A key advantage of the LT1719
is the signicant reduction in these effects, which is im-
portant whenever an LT1719 is used to detect a threshold
crossing in one direction only. In such a case, the relevant
trip point will be all that matters, and a stable offset volt-
age with an unpredictable level of hysteresis, as seen in
competing comparators, is useless. The LT1719 is many
times better than prior comparators in these regards. In
fact, the CMRR and PSRR tests are performed by check-
ing for changes in either trip point to the limits indicated
in the specications table. Because the offset voltage is
the average of the trip points, the CMRR and PSRR of the
offset voltage is therefore guaranteed to be at least as good
as those limits. This more stringent test also puts a limit
+
LT1719S8
INPUT
1719 F04
R2
VREF
R3
R1
Figure 4. Additional External Hysteresis
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