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參數(shù)資料
| 型號： | LT1713IMS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC COMP R-R IN/OUT SINGLE 8-MSOP |
| 標準包裝： | 50 |
| 系列： | UltraFast™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，補充型，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 12 V，±2.4 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 4mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 2µA @ 5V |
| 電流 - 輸出（標準）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 7.5mA |
| CMRR, PSRR（標準）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 11ns |
| 磁滯： | 100mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1323 (CN2011-ZH PDF) |
8
LT1713/LT1714
APPLICATIO S I FOR ATIO
WU
UU
Common Mode Considerations
The LT1713/LT1714 are specified for a common mode
range of – 5.1V to 5.1V on a
±5V supply, or a common
mode range of – 0.1V to 5.1V on a single 5V supply. A more
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply volt-
age. The criteria for common mode limit is that the output
still responds correctly to a small differential input signal.
When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.
Input Bias Current
Input bias current is measured with the outputs held at
2.5V with a 5V supply voltage. As with any rail-to-rail
differential input stage, the LT1713/LT1714 bias current
flows into or out of the device depending upon the com-
mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive, and these currents flow into the device. For inputs
far enough away from the supply rails, the input bias
current will be some combination of the NPN and PNP bias
currents. As the differential input voltage increases, the
input current of each pair will increase for one of the inputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.
Latch Pin Dynamics
The internal latches of the LT1713/LT1714 comparators
retain the input data (output latched) when their respective
latch pin goes high. The latch pin will float to a low state
when disconnected, but it is better to ground the latch
when a flow-through condition is desired. The latch pin is
designed to be driven with either a TTL or CMOS output.
It has built-in hysteresis of approximately 100mV, so that
slow moving or noisy input signals do not impact latch
performance. For the LT1714, if only one of the compara-
tors is being used at a given time, it is best to latch the
second comparator to avoid any possibility of interactions
between the two comparators in the same package.
High Speed Design Techniques
A substantial amount of design effort has made the
LT1713/LT1714 relatively easy to use. As with most high
speed comparators, careful attention to PC board layout
and design is important in order to prevent oscillations.
The most common problem involves power supply by-
passing which is necessary to maintain low supply im-
pedance. Resistance and inductance in supply wires and
PC traces can quickly build up to unacceptable levels,
thereby allowing the supply voltages to move as the
supply current changes. This movement of the supply
voltages will often result in improper operation. In addi-
tion, adjacent devices connected through an unbypassed
supply can interact with each other through the finite
supply impedances.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1713/LT1714
supply pins. A good high frequency capacitor, such as a
0.1
F ceramic, is recommended in parallel with a larger
capacitor, such as a 4.7
F tantalum.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LT1714 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UNDERSTANDING THE SUBJECT IS CUSTOMER SERVICE |
| LT1714CGN | 功能描述:IC COMP R-RINOUT DUAL 16-SSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| LT1714CGN#PBF | 功能描述:IC COMP R-RINOUT DUAL 16-SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 標準包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| LT1714CGN#PBF | 制造商:Linear Technology 功能描述:High Speed Comparator IC |
| LT1714CGN#TR | 功能描述:IC COMP R-R I/O DUAL LP 16SSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:UltraFast™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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