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參數(shù)資料
| 型號： | LT1713CMS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP R-R I/O SINGLE LP 8MSOP |
| 標準包裝： | 50 |
| 系列： | UltraFast™ |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，補充型，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 12 V，±2.4 V ~ 6 V |
| 電壓 - 輸入偏移（最小值）： | 4mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 2µA @ 5V |
| 電流 - 輸出（標準）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 7.5mA |
| CMRR, PSRR（標準）： | 70dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 11ns |
| 磁滯： | 100mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
4
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM
Input Voltage Range
q
– 5.1
5.1
V
CMRR
Common Mode Rejection Ratio
– 5V
≤ VCM ≤ 5V
62
70
dB
q
60
dB
PSRR+
Positive Power Supply Rejection Ratio
2.4V
≤ V+ ≤ 7V, VCM = –5V
68
80
dB
q
65
dB
PSRR–
Negative Power Supply Rejection Ratio
– 7V
≤ V– ≤ 0V, VCM = 5V
65
80
dB
q
60
dB
AV
Small-Signal Voltage Gain (Note 10)
1V
≤ VOUT ≤ 4V, RL = ∞
1.5
3
V/mV
VOH
Output Voltage Swing HIGH (Note 8)
IOUT = 1mA, VOVERDRIVE = 50mV
q
4.5
4.8
V
IOUT = 10mA, VOVERDRIVE = 50mV
q
4.3
4.6
V
VOL
Output Voltage Swing LOW (Note 8)
IOUT = – 1mA, VOVERDRIVE = 50mV
q
0.20
0.4
V
IOUT = – 10mA, VOVERDRIVE = 50mV
q
0.35
0.5
V
I+
Positive Supply Current (Per Comparator)
VOVERDRIVE = 1V
5.5
7.5
mA
q
9.0
mA
I–
Negative Supply Current (Per Comparator)
VOVERDRIVE = 1V
3.5
4.5
mA
q
5.0
mA
VIH
Latch Pin High Input Voltage
q
2.4
V
VIL
Latch Pin Low Input Voltage
q
0.8
V
IIL
Latch Pin Current
VLATCH = V+
q
10
A
tPD
Propagation Delay (Note 6)
VIN = 100mV, VOVERDRIVE = 20mV
7
10
ns
VIN = 100mV, VOVERDRIVE = 20mV
q
12
ns
VIN = 100mV, VOVERDRIVE = 5mV
8.5
ns
tPD
Differential Propagation Delay (Note 6)
VIN = 100mV, VOVERDRIVE = 20mV
0.5
3
ns
tr
Output Rise Time
10% to 90%
4
ns
tf
Output Fall Time
90% to 10%
4
ns
tLPD
Latch Propagation Delay (Note 7)
8ns
tSU
Latch Setup Time (Note 7)
1.5
ns
tH
Latch Hold Time (Note 7)
0ns
tDPW
Minimum Latch Disable Pulse Width (Note 7)
8
ns
fMAX
Maximum Toggle Frequency
VIN = 100mVP-P Sine Wave
65
MHz
tJITTER
Output Timing Jitter
VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz
15
psRMS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0
°C to 70°C. They are designed, characterized and
expected to meet specified performance from – 40
°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from – 40
°C to 85°C.
Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
Note 4: Input offset voltage (VOS) is defined as the average of the two
voltages measured by forcing first one output, then the other to V+/2.
Note 5: Input bias current (IB) is defined as the average of the two input
currents.
Note 6: Propagation delay (tPD) is measured with the overdrive added to
the actual VOS. Differential propagation delay is defined as:
tPD = tPD+ – tPD–. Load capacitance is 10pF. Due to test system
requirements, the LT1713/LT1714 propagation delay is specified with a
1k
load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (tLPD) is the delay time for the output to
respond when the latch pin is deasserted. Latch setup time (tSU) is the
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (tH) is the interval after the latch is asserted in
which the input signal must remain stable. Latch disable pulse width
(tDPW) is the width of the negative pulse on the latch enable pin that
latches in new data on the data inputs.
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