參數(shù)資料
型號: LT1619
廠商: Linear Technology Corporation
英文描述: Low Voltage Current Mode PWM Controller
中文描述: 低電壓電流模式PWM控制器
文件頁數(shù): 11/20頁
文件大?。?/td> 256K
代理商: LT1619
11
LT1619
1619fa
Here the input voltage ripple is filtered with R3, R4 and C1
so as to prevent the input ripple from falsely tripping the
LT1619 synchronization circuit. It is recommended that:
R
R
and
R
R4 1
)
f
OSC
4
1
5
3
1
||
2
3
π
(
<<
Implementation of Hysteretic UVLO
with External Synchronization
The UVLO circuit shown in Figure 10 operates down to
0.9V supply voltage. Algebraically the UVLO trip points
are:
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
LT1619
R9
510k
R7
51k
V
IN
CLK
D1
BAT85
Q2
2N2222
V
IN
UPPER TRIP POINT = 10V
V
IN
LOWER TRIP POINT = 8.4V
1619 F10
R8
30k
8.2V
R5
51k
+
R6
51k
Q1
2N2222
Figure 10. Addition of Hysteresis UVLO While Synchronizing the
LT1619. Component Values Shown are for the Upper and the
Lower V
IN
Trip Points of 10V and 8.4V. In UVLO, the Gate Drive
is Disabled by Pulling the V
C
Pin Low. Disabling the Clock Shuts
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
The collector votage of Q2 is made about 1.4V at the V
IN
lower trip voltage. This is necessary to prevent the UVLO
circuit from interfering with the feedback amplifier in the
LT1619.
Trickle Current Start from High Voltage Supplies
The low shutdown and idle mode quiescent supply cur-
rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
36V to 72V telecom bus). The trickle current start-up
circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
storage capacitor C2 during start-up. Before V
CC
reaches
the upper UVLO trip point, Q2 holds the S/S pin low. The
LT1619 draws shutdown mode current (
15
μ
A) from V
CC
.
Q2 collector can also be tied to the V
C
pin through a diode
as in Figure 10. The LT1619 will then draw idle mode
quiescent current (
140
μ
A) from V
CC
. R10 should be able
to charge C2 while supplying current to the UVLO circuit
and the LT1619. Maximizing R5 to R9 values reduces
power dissipation in R10.
When V
CC
crosses the upper UVLO threshold, the LT1619
starts switching and its current consumption increases.
Before the bootstrap takes over, the LT1619 draws its
current from C2. V
CC
ramps towards the lower UVLO
threshold. Increasing the value of C2 allows more time for
the bootstrap circuit to establish itself before the converter
enters undervoltage lockout.
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
LT1619
BOOTSTRAP
WINDING
T1
D2
R9
R7
V
CC
HV V
IN
Q2
1619 F11
R8
C2
R10
R5
R6
Q1
Figure 11. Trickle Current Start-Up with Bootstrapped V
CC
V
V
V
R
R
R
and
V
R
R
(
R
R
V
V
R
R
(
6
R
R
R
R
(
5
7
7
R
UVLOHysteresis
V
V
R
R
(
R
R
R
+
V
)
V
R
R
R
INH
Z
BE
INL
Z
BE
INH
INL
Z
BE
=
+
+
=
+
)
+
+
)
+
)
=
=
+
|| R
+
9
+
1
5
6
7
5
7
9
5
5
7
9
5
7
9
5
5
9
R
5
6
7
||
||
||
||
||
||
R
6
APPLICATIOU
W
U
U
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