The q denotes the specifications which apply over the full operating
參數(shù)資料
型號(hào)： LT1568IGN
廠商： Linear Technology
文件頁數(shù)： 10/16頁
文件大?。?/td> 0K
描述： IC BLOCK BUILD FLTR LONOS 16SSOP
標(biāo)準(zhǔn)包裝： 100
濾波器類型： 帶通
頻率 - 截止或中心： 200kHz
濾波器數(shù)： 2
濾波器階數(shù)： 2nd
電源電壓： 2.7 V ~ 11 V，±2.7 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
LT1568
3
1568f
The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications and typical values are at TA = 25°C. VS = single 5V, EN pin to logic “l(fā)ow,” RL = 400,
connected to midsupply, RFIL = R11 = R21 = R31 = R12 = R22 = R32, unless otherwise noted (see Block Diagram).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IB
Op Amp Input Bias Current
VS = 3V
q
0.5
2
A
VS = 5V
q
0.4
2
A
VS = ±5V
q
–0.2
2
A
Inverter Bandwidth (Note 4)
55
MHz
Inverter Gain (Sections A and B, Note 5)
Frequency = DC
q
–0.2
0.01
0.2
dB
Frequency = 2MHz
0.01
dB
Frequency = 10MHz
0.27
dB
Inverter Phase Shift (Sections A and B,
Frequency = DC
180
DEG
Note 5)
Frequency = 2MHz
179
DEG
Frequency = 10MHz
176
DEG
SR
Slew Rate (OUTA, OUTB, OUTA,
53
V/
s
OUTB) Pins
VCM
Common Mode Input Voltage Range
VS = 3V
1 to 1.9
V
(GNDA and GNDB Pins, Note 6)
VS = ±5V
–3.4 to 2.7
V
Single Supply GND Reference Voltage
VS = 5V, GNDA Tied to GNDB
2.5
V
VIL
EN Input Logic Low Level
VS = 3V, 5V or ±5V
q
V+ – 2.1
V
VIH
EN Input Logic High Level
VS = 3V, 5V or ±5V
q
V+ – 0.6
V
EN Input Pull-Up Resistor
30
40
k
tDIS
Disable (Shutdown) Time
EN Pin Steps from 0V to V+
20
s
tEN
Enable (Start-Up) Time
EN Pin Steps from V+ to 0V
100
s
ELECTRICAL CHARACTERISTICS
Specifications are for the output (OUTA or OUTB) of a
single 2nd order section (A or B) with respect to VGND = VGNDA = VGNDB,
gain = –1, RFIL = R11 = R21 = R31 = R12 = R22 = R32, (see Block Diagram). The q denotes the specifications which apply over the
full operating temperature range, otherwise specifications and typical values are at TA = 25°C. VS = single 5V, EN pin to logic “l(fā)ow,”
RL = 400, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC
DC Gain
q
–1.01
–1
–0.99
V/V
VOS(OUT)
DC Offset Voltage
VS = 3V, fC = 1MHz, RFIL = 1.28k
q
–5
2.6
15
mV
(VOUTA – VGNDA) or (VOUTB – VGNDB)VS = 5V, fC = 1MHz, RFIL = 1.28k
q
–10
0.6
10
mV
VS = ±5V, fC = 1MHz, RFIL = 1.28k
q
–12
–4.0
4
mV
VOS(OUT)
DC Offset Voltage Mismatch
VS = 3V, fC = 1MHz, RFIL = 1.28k
q
–8
±48
mV
(VOUTA – VGNDA) – (VOUTB – VGNDB)VS = 5V, VS = ±5V, fC = 1MHz, RFIL = 1.28k
q
–10
±410
mV
Transfer Function Characteristics for Each Section (A or B) to Single-Ended Output (OUTA or OUTB)
fC
Cutoff Frequency Range (Note 7)
VS = 3V, VS = 5V, VS = ±5V
q
0.2
10
MHz
TC
Cutoff Frequency Temperature Coefficient
q
±1
ppm/
°C
FILTER ELECTRICAL CHARACTERISTICS
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