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參數(shù)資料
| 型號： | LT1507IS8-3.3 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 3 A SWITCHING REGULATOR, 570 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 343K |
| 代理商： | LT1507IS8-3.3 |
18
LT1507
APPLICATIO
S I
FOR
ATIO
U
Example: with V
IN
= 5V, V
OUT
= 3.3V, I
OUT
= 1A;
W
U
U
P
W
P
W
P
W
SW
BOOST
Q
=
+
(
)
.
( )( )
(
)
=
+
=
=
+
3 3 0 005
=
.
0 032
=
+
=
( . )() ( . )
0 4 1
5
0 26
.
.
( . )
3 3
5
.
( .
50 003
)
. ( .
)
3 3
16 10
0 04
2
0 3
0.
1
75
0 046
9
3
Total power dissipation is 0.3 + 0.046 + 0.032 = 0.38W.
Thermal resistance for the LT1507 packages is influenced
by the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 120
°
C/W. No plane will increase resistance to about
150
°
C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature;
T
J
= T
A
+
θ
JA
(P
TOT
)
With the S8 package (
θ
JA
= 120
°
C/W) at an ambient
temperature of 70
°
C;
T
J
= 70 + 120(0.38) = 116
°
C
FREQUENCY COMPENSATION
The LT1507 uses a “current mode” architecture to help
alleviate phase shift created by the inductor. The basic
connections are shown in Figure 9. Gain of the power stage
can be modeled as 1.8A/V transconductance from the V
C
pin voltage to current delivered to the output. This is
shown in Figure 8 where the transconductance from V
C
pin to inductor current is essentially flat from 50Hz to
50kHz and phase shift is minimal in the important loop
unity-gain band of 1kHz to 50kHz. Inductor variation from
3
μ
H to 20
μ
H will have very little effect on these curves.
Overall gain from the V
C
pin to output is then modeled as
the product of 1.8A/V transconductance multiplied by the
complex impedance of the load in parallel with the output
capacitor model.
The error amplifier can be modeled as a transconductance
of 2000
μ
mho, with an output impedance of 200k
in
FREQUENCY (Hz)
G
C
2.0
1.5
1.0
0.5
0
P
C
°
)
80
40
0
–40
–80
10
1k
10k
100k
LT1507 F08
100
GAIN (A/V)
PHASE
V
OUT
= 3.3V
I
OUT
= 250mA
V
= 5V
L = 10
μ
H
Figure 8. Phase and Gain from V
C
Pin Voltage
to Inductor Current
POWER STAGE
g
m
= 1.8A/V
ERROR AMPLIFIER
g
m
= 2000
μ
ho
200k
2.42V
LT1507
R
C
C
C
C
F
GND
V
C
V
SW
L1
F
B
R1
R2
ESR
+
OUTPUT
1507 F09
–
+
C1
12pF
Figure 9. Small-Signal Model for Loop Stability Analysis
parallel with 12pF. In all practical applications, the com-
pensation network from V
C
pin to ground has a much
lower impedance than the output impedance of the ampli-
fier at frequencies above 500Hz. This means that the error
amplifier characteristics themselves do not contribute
excess phase shift to the loop and the phase/gain charac-
teristics of the error amplifier section are completely
controlled by the external compensation network.
The complete small-signal model is shown in Figure 9. R1
and R2 are the divider used to set output voltage. These are
internal on the fixed voltage LT1507-3.3 with R1 = 1.8k
and R2 = 5k. R
C
, C
C
and C
F
are external compensation
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