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參數(shù)資料
| 型號： | LT1432CS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 5V High Efficiency Step-Down Switching Regulator Controller |
| 中文描述： | SWITCHING CONTROLLER, PDSO8 |
| 封裝： | PLASTIC, SO-8 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 611K |
| 代理商： | LT1432CS8 |
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8
LT1432
U
S
A
O
PPLICATI
U
U
FET Switch Loss
V
V
R
I
V
IN–
OUT
SW
OUT
IN
2
=
(
)(
)(
)
(Ignoring gate drive power)
The change in efficiency is:
Diode Loss – FET Loss Efficiency
V
V
IN
This is equal to:
OUT
2
(
)
(
)(
)
V – V
V –R
V
IN
I
)( )
V
OUT
FET
OUT
OUT
(
)
(
×
)
(
)(
If V
F
(diode forward voltage) = 0.45V, V
IN
= 10V, V
OUT
= 5V,
R
FET
= 0.1
, I
OUT
= 1A, and efficiency = 90%, the improve-
ment in efficiency is only:
(
(
This does not take FET gate drive losses into account,
which can easily reduce this figure to less than 2%. The
added cost, size, and complexity of a synchronous switch
configuration would be warranted only in the most ex-
treme circumstances.
Burst mode efficiency is limited by quiescent current drain
in the LT1432 and the switching IC. The typical burst mode
zero-load input power is 27mW. This gives about one
month battery life for a 12V, 1.2AHr battery pack. Increas-
ing load power reduces discharge time proportionately.
Full shutdown current is only about 15
μ
A, which is consid-
erably less than the self-discharge rate of typical batteries.
10V – 5V 0.45V – 0.1
)
1A 0.9
10V 5V
2.8%
2
×
(
)
=
Burst Mode Operation
Burst mode is initiated by allowing the mode pin to float,
where it will assume a DC voltage of approximately 1V. If
AC pickup from surrounding logic lines is likely, the mode
pin should be bypassed with a 200pF capacitor. Burst
mode is used to reduce quiescent operating current when
the regulator output current is very low, as in “sleep” mode
in a lap-top computer. In this mode, hysteresis is added to
the error amplifier to make it switch on and off, rather than
maintain a constant amplifier output. This forces the
switching IC to either provide a rapidly increasing current
or to go into full micropower shutdown. Current is deliv-
ered to the output capacitor in pulses of higher amplitude
and low duty cycle rather than a continuous stream of low
amplitude pulses. This maximizes efficiency at light load
by eliminating quiescent current in the switching IC during
the period between bursts.
The result of pulsating currents into the output capacitor
is that output ripple amplitude increases, and ripple fre-
quency becomes a function of load current. The typical
output ripple in burst mode is 150mVp-p, and ripple
frequency can vary from 50Hz to 2kHz. This is not normally
a problem for the logic circuits which are kept “alive”
during sleep mode.
Some thought must be given to proper sequencing be-
tween normal mode and burst mode. A heavy (>100mA)
load in burst mode can cause excessive output ripple, and
an abnormally light load (10mA to 30mA, see curves) in
normal mode can cause the regulator to revert to a quasi-
burst mode that also has higher output ripple. The worst
condition is a sudden, large increase in load current
(>100mA) during this quasi-burst mode or just after a
switch from burst mode to normal mode. This can cause
the output to sag badly while the regulator is establishing
normal mode operation (
≈
100
μ
s). To avoid problems, it is
suggested that the power-down sequence consist of re-
ducing load current to below 100mA, but greater than the
minimum for normal mode, then switching to burst mode,
followed by a reduction of load current to the final sleep
value. Power-up would consist of increasing the load
current to the minimum for normal mode, then switching
to normal mode, pausing for 1ms, followed by return to
full load.
If this sequence is not possible, an alternative is to
minimize normal mode settling time by adding a 47k
resistor between V
+
and V
C
pins. The output capacitor
should be increased to >680
μ
F and the compensation
capacitors should also be as small as possible, consistent
with adequate phase margin. These modifications will
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