參數(shù)資料
型號: LT1359CN
廠商: LINEAR TECHNOLOGY CORP
元件分類: 運動控制電子
英文描述: OCTAL BUFFERS AND LINE DRIVERS 20-SOIC 0 to 70
中文描述: QUAD OP-AMP, 800 uV OFFSET-MAX, 22 MHz BAND WIDTH, PDIP14
封裝: 0.300 INCH, PLASTIC, DIP-14
文件頁數(shù): 10/12頁
文件大?。?/td> 259K
代理商: LT1359CN
10
LT1358/LT1359
Because of variation in the matching of NPN and PNP beta,
the polarity of the input bias current can be positive or
negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized.
The inputs can withstand transient differential input volt-
ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
sustained differential inputs, the average supply current
will increase, excessive power dissipation will result and
the part may be damaged.
The part should not be used as
a comparator, peak detector or other open-loop applica-
tion with large, sustained differential inputs
. Under
normal, closed-loop operation, an increase of power dis-
sipation is only noticeable in applications with large slewing
outputs and is proportional to the magnitude of the
differential input voltage and the percent of the time that
the inputs are apart. Measure the average supply current
for the application in order to calculate the power dissipa-
tion.
Circuit Operation
The LT1358/LT1359 circuit topology is a true voltage
feedback amplifier that has the slewing behavior of a
current feedback amplifier. The operation of the circuit can
be understood by referring to the simplified schematic.
The inputs are buffered by complementary NPN and PNP
emitter followers which drive a 500
resistor. The input
voltage appears across the resistor generating currents
which are mirrored into the high impedance node. Comple-
mentary followers form an output stage which buffers the
gain node from the load. The bandwidth is set by the input
resistor and the capacitance on the high impedance node.
The slew rate is determined by the current available to
charge the gain node capacitance. This current is the
differential input voltage divided by R1, so the slew rate is
proportional to the input. Highest slew rates are therefore
seen in the lowest gain configurations. For example, a 10V
output step in a gain of 10 has only a 1V input step,
whereas the same output step in unity gain has a 10 times
APPLICATIO
S I
FOR
ATIO
U
W
U
U
greater input step. The curve of Slew Rate vs Input Level
illustrates this relationship. The LT1358/LT1359 are tested
for slew rate in a gain of –2 so higher slew rates can be
expected in gains of 1 and –1, and lower slew rates in
higher gain configurations.
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a
capacitive load (or a low value resistive load) the network
is incompletely bootstrapped and adds to the compensa-
tion at the high impedance node. The added capacitance
slows down the amplifier which improves the phase
margin by moving the unity-gain frequency away from the
pole formed by the output impedance and the capacitive
load. The zero created by the RC combination adds phase
to ensure that even for very large load capacitances, the
total phase lag can never exceed 180 degrees (zero phase
margin) and the amplifier remains stable.
Power Dissipation
The LT1358/LT1359 combine high speed and large output
drive in small packages. Because of the wide supply
voltage range, it is possible to exceed the maximum
junction temperature under certain conditions. Maximum
junction temperature (T
J
) is calculated from the ambient
temperature (T
A
) and power dissipation (P
D
) as follows:
LT1358CN8: T
J
= T
A
+ (P
D
x 130
°
C/W)
LT1358CS8: T
J
= T
A
+ (P
D
x 190
°
C/W)
LT1359CN: T
J
= T
A
+ (P
D
x 110
°
C/W)
LT1359CS: T
J
= T
A
+ (P
D
x 150
°
C/W)
Worst case power dissipation occurs at the maximum
supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
1/2 supply voltage). For each amplifier P
DMAX
is:
P
DMAX
= (V
+
– V
)(I
SMAX
) + (V
+
/2)
2
/R
L
Example: LT1358 in S8 at 70
°
C, V
S
=
±
15V, R
L
= 500
P
DMAX
= (30V)(2.9mA) + (7.5V)
2
/500
= 200mW
T
JMAX
= 70
°
C + (2 x 200mW)(190
°
C/W) = 146
°
C
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