參數(shù)資料
型號(hào): LT1339
廠商: Linear Technology Corporation
英文描述: High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
中文描述: 高效率,同步,四開(kāi)關(guān)降壓升壓控制器
文件頁(yè)數(shù): 15/20頁(yè)
文件大?。?/td> 415K
代理商: LT1339
15
LT1339
APPLICATIO
S I
FOR
ATIO
U
The maximum power loss terms for the switches are thus:
P
MAIN
= (DC)(I
MAX
)
2
(1 +
δ
)(R
DS(ON)
) +
2(V
IN
)
2
(I
MAX
)(C
RSS
)(f
O
)
P
SYNC
= (1 – DC)(I
MAX
)
2
(1 +
δ
)(R
DS(ON)
)
The (1 +
δ
) term in the above relations is the temperature
dependency of R
DS(ON)
, typically given in the form of a
normalized R
DS(ON)
vs Temperature curve in a MOSFET
data sheet.
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT1339, causing a negative voltage in
excess of the Absolute Maximum Rating to be imposed on
that pin. Connection of a catch Schottky (rated to about 1A
is typically sufficient) from this pin to ground will eliminate
this effect.
W
U
U
V
OUT
I
L
{ESR + [(4)(f
O
)
C
OUT
]
–1
}
where f
O
= operating frequency.
Efficiency Considerations and Heat Dissipation
High output power applications have inherent concerns
regarding power dissipation in converter components.
Although high efficiencies are achieved using the LT1339,
the power dissipated in the converter climbs to relatively
high values when the load draws large amounts of power.
Even at 90% efficiency, an application that provides 500W
to the load has conversion loss of 55W.
I
2
R dissipation through the switches, sense resistor and
inductor series resistance create substantial losses under
high currents. Generally, the dominant I
2
R loss is evident
in the FET switches. Loss in each switch is proportional to
the conduction time of that switch. For example, in a 48V
to 5V converter the synchronous FET conducts load cur-
rent for almost 90% of the cycle time and thus, requires
greater consideration for dissipating I
2
R power.
Gate charge/discharge current creates additional current
drain on the 12V supply. If powered from a high voltage
input through a linear regulator, the losses in that regula-
tor device can become significant. A supply solution
bootstrapped from the output would draw current from a
lower voltage source and reduce this loss component.
Transition losses are significant in the topside switch FET
when high V
IN
voltages are used. Transition losses can be
estimated as:
P
TLOSS
2(V
IN
)
2
(I
MAX
)(C
RSS
)(f
O
)
Since the conduction time in the main switch of a 48V to
5V converter is small, the I
2
R loss in the main switch FET
is also small. However, since the FET gate must switch up
past the 48V input voltage, transition loss can become a
significant factor. In such a case, it is often prudent to take
the increased I
2
R loss of a smaller FET in order to reduce
C
RSS
and thus, the associated transition losses.
Gate Drive Buffers
The LT1339 is designed to drive relatively large capacitive
loads. However, in certain applications, efficiency im-
provements can be realized by adding an external buffer
stage to drive the gates of the FET switches. When the
C
IN
and C
OUT
Supply Decoupling Capacitor Selection
The large currents typical of LT1339 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
operation, the source current of the main switch MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. Most of this
current is provided by the input bypass capacitor. To
prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
)
I
I
V
V
V
V
RMS
MAX
OUT
IN
OUT
IN
(
(
)
(
)
/ 2
which peaks at a 50% duty cycle, when I
RMS
= I
MAX
/2.
Capacitor ripple current ratings are often based on only
2000 hours (three months) lifetime; it is advisable to
derate either the ESR or temperature rating of the capaci-
tor for increased MTBF of the regulator.
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
peak ripple current is equal to that in the inductor (
I
L
),
typically a fraction of the load current. C
OUT
is selected to
reduce output voltage ripple to a desirable value given an
expected output ripple current. Output ripple (
V
OUT
) is
approximated by:
相關(guān)PDF資料
PDF描述
LT1339CN Octal Buffers/Drivers With 3-State Outputs 20-SOIC 0 to 70
LT1339CSW Octal Buffers/Drivers With 3-State Outputs 20-SOIC 0 to 70
LT1339I Octal Buffers/Drivers With 3-State Outputs 20-SOIC 0 to 70
LT1339IN Octal Buffers/Drivers With 3-State Outputs 20-PDIP 0 to 70
LT1339ISW High Power Synchronous DC/DC Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LT1339C 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:High Power Synchronous DC/DC Controller
LT1339CN 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤(pán) 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱(chēng):LM1771SSDX
LT1339CN#PBF 功能描述:IC REG CTRLR BST PWM CM 20-DIP RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:50% 電源電壓:9 V ~ 10 V 降壓:無(wú) 升壓:是 回掃:是 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 包裝:帶卷 (TR)
LT1339CN#PBF 制造商:Linear Technology 功能描述:DC-DC CONTROLLER CURRENT MODE 制造商:Linear Technology 功能描述:DC-DC CONTROLLER, CURRENT MODE, 150KHZ,
LT1339CSW 功能描述:IC REG CTRLR BST PWM CM 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤(pán) 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱(chēng):LM1771SSDX