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參數(shù)資料
| 型號： | LT1224CS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 0K |
| 描述： | IC OP-AMP HI-SPEED 45MHZ 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 400 V/µs |
| 增益帶寬積： | 45MHz |
| 電流 - 輸入偏壓： | 4µA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
LT1224
6
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
The LT1224 may be inserted directly into HA2541, HA2544,
AD847, EL2020 and LM6361 applications, provided that
the nulling circuitry is removed. The suggested nulling
circuit for the LT1224 is shown below.
Offset Nulling
–
+
3
2
1
8
5k
0.1
F
7
6
4
0.1
F
V+
V –
LT1224
LT1224 TA03
Layout and Passive Components
As with any high speed operational amplifier, care must be
taken in board layout in order to obtain maximum perfor-
mance. Key layout issues include: use of a ground plane,
minimization of stray capacitance at the input pins, short
lead lengths, RF-quality bypass capacitors located close
to the device (typically 0.01
F to 0.1F), and use of low
ESR bypass capacitors for high drive current applications
(typically 1
F to 10F tantalum). Sockets should be
avoided when maximum frequency performance is
required, although low profile sockets can provide
reasonable performance up to 50MHz. For more details
see Design Note 50. Feedback resistor values greater than
5k are not recommended because a pole is formed with the
input capacitance which can cause peaking. If feedback
resistors greater than 5k are used, a parallel
capacitor of 5pF to 10pF should be used to cancel the input
pole and optimize dynamic performance.
Transient Response
The LT1224 gain bandwidth is 45MHz when measured at
f = 1MHz. The actual frequency response in unity-gain is
considerably higher than 45MHz due to peaking caused by
a second pole beyond the unity-gain crossover. This is
reflected in the 50
° phase margin and shows up as
overshoot in the unity-gain small-signal transient re-
sponse. Higher noise gain configurations exhibit less
overshoot as seen in the inverting gain of one response.
Small Signal, AV = 1
Small Signal, AV = –1
The large-signal responses in both inverting and non-
inverting gain show symmetrical slewing characteristics.
Normally the noninverting response has a much faster
rising edge than falling edge due to the rapid change in
input common-mode voltage which affects the tail current
of the input differential pair. Slew enhancement circuitry
has been added to the LT1224 so that the noninverting
slew rate response is balanced.
Large Signal, AV = 1
Large Signal, AV = –1
Input Considerations
Resistors in series with the inputs are recommended for
the LT1224 in applications where the differential input
voltage exceeds
±6V continuously or on a transient basis.
An example would be in noninverting configurations with
high input slew rates or when driving heavy capacitive
loads. The use of balanced source resistance at each input
is recommended for applications where DC accuracy must
be maximized.
LT1224 TA04
LT1224 TA06
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