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參數(shù)資料
| 型號： | LT1224CS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP-AMP HI-SPEED 45MHZ 8SOIC |
| 標準包裝： | 100 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉換速率： | 400 V/µs |
| 增益帶寬積： | 45MHz |
| 電流 - 輸入偏壓： | 4µA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 15 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1318 (CN2011-ZH PDF) |
3
LT1224
VS = ±5V, TA = 25°C, RL = 1k, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
VS = ±15V, (Note 2)
1
4
mV
VS = ±5V, (Note 2)
2
5
mV
Input VOS Drift
25
V/°C
IOS
Input Offset Current
VS = ±15V and VS = ±5V
100
600
nA
IB
Input Bias Current
VS = ±15V and VS = ±5V
4
9
A
CMRR
Common-Mode Rejection Ratio
VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V
83
98
dB
PSRR
Power Supply Rejection Ratio
VS = ±5V to ±15V
73
84
dB
AVOL
Large-Signal Voltage Gain
VS = ±15V, VOUT = ±10V, RL = 500
2.5
7
V/mV
VS = ±5V, VOUT = ±2.5V, RL = 500
2.0
7
V/mV
VOUT
Output Swing
VS = ±15V, RL = 500±12.0
±13.3
V
VS = ±5V, RL = 500 or 150±3.0
±3.3
V
IOUT
Output Current
VS = ±15V, VOUT = ±12V
24
40
mA
VS = ±5V, VOUT = ±3V
20
40
mA
SR
Slew Rate
VS = ±15V, AVCL = –2, (Note 3)
250
400
V/
s
IS
Supply Current
VS = ±15V and VS = ±5V
7
10.5
mA
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
(Note 2)
1
4
mV
IOS
Input Offset Current
100
400
nA
IB
Input Bias Current
48
A
Input Voltage Range +
2.5
4
V
Input Voltage Range –
– 3
– 2.5
V
CMRR
Common-Mode Rejection Ratio
VCM = ±2.5V
86
98
dB
AVOL
Large-Signal Voltage Gain
VOUT = ±2.5V, RL = 500
2.5
7
V/mV
VOUT = ±2.5V, RL = 150
3
V/mV
VOUT
Output Swing
RL = 500±3.0
±3.7
V
RL = 150±3.0
±3.3
V
IOUT
Output Current
VOUT = ±3V
20
40
mA
SR
Slew Rate
AVCL = –2, (Note 3)
250
V/
s
Full Power Bandwidth
3V Peak, (Note 4)
13.3
MHz
GBW
Gain-Bandwidth
f = 1MHz
34
MHz
tr, tf
Rise Time, Fall Time
AVCL = 1, 10% to 90%, 0.1V
7
ns
Overshoot
AVCL = 1, 0.1V
20
%
Propagation Delay
50% VIN to 50% VOUT
7ns
ts
Settling Time
–2.5V to 2.5V, 0.1%
90
ns
IS
Supply Current
79
mA
ELECTRICAL C
C
HARA TERISTICS
ELECTRICAL C
C
HARA TERISTICS 0°C ≤ T
A ≤ 70°C, RL = 1k, VCM = 0V unless otherwise noted.
Note 1: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Note 2: Input offset voltage is tested with automated test equipment
in <1 second.
Note 3: Slew rate is measured in a gain of –2 between
±10V on the output
with
±6V on the input for ±15V supplies and ±2V on the output with
±1.75V on the input for ±5V supplies.
Note 4: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2
πVp.
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