參數(shù)資料
型號: LT1186F
廠商: Linear Technology Corporation
英文描述: 9-Bit Odd/Even Parity Generators/Checkers 14-PDIP 0 to 70
中文描述: DAC的可編程冷陰極開關(guān)穩(wěn)壓器(位到NitsTM)
文件頁數(shù): 12/16頁
文件大?。?/td> 206K
代理商: LT1186F
12
LT1186F
APPLICATIO
S I
FOR
ATIO
U
circuitry provides a ratio of switch current to driver current
of about 50:1.
W
U
U
8-Bit Current Output DAC
The 8-bit current output DAC is guaranteed monotonic and
is digitally adjustable by the 8-bit counter in 256 equal
steps. On power up, the counter resets to 80H and the DAC
assumes its mid-range value. The current output I
OUT
drives the I
CCFL
pin and sets control current for the lamp
current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50
μ
A
±
6%.
Digital Interface
On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until V
CC
resets. On power-up in pulse
mode, a logic high at D
IN
puts the counter into increment-
only mode. If UP/DN (D
IN
) is ever pulled low, the counter
configures into increment/decrement mode until V
CC
re-
sets. These modes are illustrated in Figure 1.
SINGLE DAC
SPI MODE
PULSE MODE
LT1186F F01a
INCREMENT/
DECREMENT
INCREMENT-
ONLY
CS STAYS
HIGH
CS EVER
GOES LOW
D
(UP/DN)
EVER GOES
LOW
D
STAYS
HIGH
Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)
Figure 1b. SPI Mode Setup
POWER ON
V
CC
LT1186F F01b
CS
CS EVER GOES LOW
POWER ON
V
CC
LT1186F F01c
CS ALWAYS HIGH
D
IN
ALWAYS HIGH
Figure 1c. Pulse Mode Setup (Increment Only)
POWER ON
V
CC
CS ALWAYS HIGH
LT1186F F01d
UP/DN
UP/DN EVER GOES LOW
Figure 1d. Pulse Mode Setup (Increment/Decrement)
Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, D
OUT
comes out of three-state.
The clock (CLK) synchronizes the data transfer. Each input
bit shifts into D
IN
beginning with the MSB on the rising CLK
edge and each previous data bit shifts out of D
OUT
begin-
ning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
I
OUT
= (8-bit serial input data)(50
μ
A)/255 and the D
OUT
pin
returns to a high impedance state.
1-Wire Interface (Pulse Mode)
In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. I
OUT
= (B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
)
(50
μ
A)/255. The upper 6-bit counter = B
7
B
6
B
5
B
4
B
3
B
2
and
B
1
= B
0
= 0. To configure the LT1186F into increment-only
mode, tie CS and D
IN
to V
CC
.
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