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參數(shù)資料
| 型號： | LT1169 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp |
| 中文描述： | 雙低噪聲，Picoampere偏置電流，JFET輸入運算放大器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 333K |
| 代理商： | LT1169 |
4
LT1169
ELECTRICAL C
HARA TERISTICS
V
S
=
±
15V, V
CM
= 0V, –40
°
C
≤
T
A
≤
85
°
C, (Note 7), unless otherwise noted.
SYMBOL
V
OS
I
B+
CMRR
PSRR
PARAMETER
Offset Voltage Match
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
CONDITIONS (Note 1)
MIN
TYP
1.8
10
93
92
MAX
6
180
UNITS
mV
G
G
pA
dB
dB
(Note 8)
(Note 8)
G
73
75
G
The
G
denotes specifications which apply over the full operating
temperature range.
Note 1:
Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op
amps) typically 120 op amps will be better than the indicated specification.
Note 2:
I
B
and I
OS
readings are extrapolated to a warmed-up temperature
from 25
°
C measurements and 45
°
C characterization data.
Note 3:
Current noise is calculated from the formula:
i
n
= (2qI
B
)
1/2
where q = 1.6
×
10
–19
coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 4:
Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.8mV.
Note 5:
This parameter is not 100% tested.
Note 6:
Slew rate is measured in A
V
= –1; input signal is
±
7.5V, output
measured at
±
2.5V.
Note 7:
The LT1169 is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40
°
C and 85
°
C.
Guaranteed I grade parts are available; consult factory.
Note 8:
CMRR and
PSRR are defined as follows:
(1) CMRR and PSRR are measured in
μ
V/V on the individual
amplifiers.
(2) The difference is calculated between the matching sides in
μ
V/V.
(3) The result is converted to dB.
Note 9:
The LT1169 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed-up chip
temperature can be 10
°
C to 50
°
C higher than the ambient temperature.
C
HARA TERISTICS
U
A
TYPICAL PERFOR
CE
Voltage Noise vs Frequency
0.1Hz to 10Hz Voltage Noise
TIME (SEC)
V
μ
V
2
4
6
8
LT1169 TPC01
10
0
FREQUENCY (Hz)
1
10
1
10
100
100
1k
10k
LT1169 TPC03
R
√
H
T
A
= 25°C
V
S
= ±15V
1/f CORNER
60Hz
TYPICAL
INPUT VOLTAGE NOISE (nV/
√
Hz)
4.2
P
30
40
50
7.4
LT1169 TPC02
20
10
0
5.0
5.8
6.6
4.6
7.8
5.4
6.2
7.0
8.2
T
A
= 25
°
C
V
S
=
±
15V
510 OP AMPS TESTED
1kHz Input Noise Voltage
Distribution
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| LT1169CN8#PBF | 功能描述:IC OPAMP JFET LOWNOISE DUAL 8DIP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
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