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參數(shù)資料
| 型號(hào)： | LT1122DS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP JFET FAST-SETTLE 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 75 V/µs |
| 增益帶寬積： | 13MHz |
| 電流 - 輸入偏壓： | 12pA |
| 電壓 - 輸入偏移： | 130µV |
| 電流 - 電源： | 7.8mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
LT1122
8
1122fb
For more information www.linear.com/LT1122
APPLICATIONS INFORMATION
Settling Time Measurements
Settling time test circuits shown on some competitive
devices’ data sheets require:
1. A“flattop”pulsegenerator.Unfortunately,flattoppulse
generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four-to-one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
3. A small inductor load to optimize settling.
TheLT1122’ssettlingtimeis100%testedinthetestcircuit
shown. No “flat top” pulse generator is required. The test
circuit can be readily constructed, using commercially
available ICs. Of course, standard high frequency board
construction techniques should be followed. All LT1122s
are measured with a constant feedback capacitor. No fine
tuning is required.
Speed Boost/Overcompensation Terminal
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting Pin 8 to the posi-
tive supply (Pin 7) increases slew rate and bandwidth by
about 25%, but at the expense of a reduction in phase
marginbyapproximately18degrees.Unity-gaincapacitive
load handling decreases from typically 500pF to 100pF.
Conversely,connectinga15kresistorfromPin8toground
pulls 1mA out of Pin 8 (with V+ = 15V). This reduces slew
rate and bandwidth by 25%. Phase margin and capacitive
load handling improve; the latter typically increasing to
800pF.
High Speed Operation
As with most high speed amplifiers, care should be
taken with supply decoupling, lead dress and component
placement.
ThepowersupplyconnectionstotheLT1122mustmaintain
a low impedance to ground over a bandwidth of 20MHz.
This is especially important when driving a significant
resistive or capacitive load, since all current delivered to
the load comes from the power supplies. Multiple high
qualitybypasscapacitorsarerecommendedforeachpower
supply line in any critical application. A 0.1F ceramic and
a 1F electrolytic capacitor, as shown, placed as close as
possible to the amplifier (with short lead lengths to power
supply common) will assure adequate high frequency
bypassing, in most applications.
V+
7
2
6
3
4
1F
0.1F
1F
0.1F
V–
LT1122
1122 TA03
+
–
+
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed-loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capaci-
tor (CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
RS
CS
CIN
RF
CF
OUTPUT
+
–
1122 TA04
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