參數(shù)資料
型號: LT1116CS8
廠商: Linear Technology
文件頁數(shù): 6/8頁
文件大?。?/td> 0K
描述: IC COMPARATOR 12NS SINGLE 8SOIC
標(biāo)準(zhǔn)包裝: 100
系列: UltraFast™
類型: 帶鎖銷
元件數(shù): 1
輸出類型: CMOS,補充型,TTL
電壓 - 輸入偏移(最小值): 3mV @ 5V
電流 - 輸入偏壓(最小值): 20µA @ 5V
電流 - 輸出(標(biāo)準(zhǔn)): 20mA
電流 - 靜態(tài)(最大值): 38mA
CMRR, PSRR(標(biāo)準(zhǔn)): 90dB CMRR,75dB PSRR
傳輸延遲(最大): 16ns
工作溫度: 0°C ~ 70°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
LT1116
6
1116fb
Common Mode Considerations
The LT1116 is specified for a common mode range of 0V
to 2.5V with a single 5V supply, and –5V to 2.5V with
±5V
supplies. The common mode range is defined as the DC
input for which the output responds correctly to small
changes in the input differential. Input signals can exceed
the positive common mode limit up to the 15V absolute
maximum rating without damaging the comparator. There
will, however, be an increase in propagation delay of up to
10ns when the input signal switches back into the
common mode range. When input signals fall below the
negative common mode limit, the internal PN diode formed
with the substrate can turn on (resulting in significant
charge flow throughout the die). A Schottky clamp diode,
between the input and the negative rail, speeds up recov-
ery from negative overdrive by preventing the substrate
diode from turning on. The zero crossing detector in
Figure 1 demonstrates the use of a fast clamp diode.
Recovery, from 500mV overdrive below V, for this circuit
is approximately 18ns.
Input Characteristics
Each input to the LT1116 is buffered with a fast PNP
follower—input bias current therefore does not vary
significantly throughout the common mode range. When
either input exceeds the positive common mode limit, the
bias current drops to zero. Inputs that fall more than one
diode and drop below Vwill forward bias the substrate or
clamp diode, causing large input current to flow.
Single ended input resistance is about 5M
, and remains
roughly constant over the input common mode range. The
common mode resistance is about 2.5M
with zero
differential input voltage, and does not change
significantly with the absolute value of differential input.
Effective input capacitance, typically 5pF, is determined by
measuring the resulting change in propagation delay for a
1k
change in source resistance.
Latch Pin Dynamics
The internal latch uses local regenerative feedback to
shorten set-up and hold times. Driving the latch pin high
retains the output state. The latch pin floats to a high state
when disconnected, so it must be driven low for
flow-through operation. The set-up time required to
guarantee detecting a given transition of the inputs is 2ns.
The inputs must also remain stable for a 2ns hold time
after latch is asserted. New data will appear at the output
approximately 10ns to 12ns after the latch goes low. The
latch pin has no built-in hysteresis, and is designed to be
driven from TTL or CMOS logic gates.
Additional Information
Linear Technology’s Application Note 13 provides an
extensive discussion of design techniques for high speed
comparators.
Figure 1. The Zero Crossing Detector Terminates the
Transmission Line At Its 50
Characteristic Impedance. Negative
Inputs Should Not Fall Below –2V to keep the Signal Current
Within the Clamp Diode’s Maximum Forward Rating. Positive
Inputs Should not Exceed the Devices Absolute Maximum Ratings
nor the Power Rating on the Terminating Resistor
Figure 2. This Single Supply Crystal Oscillator Utilizes Crystals
From 10MHz To 15MHz Without Component Changes
APPLICATIO S I FOR ATIO
WU
UU
Fast Zero Crossing Detector
Single Supply Crystal Oscillator 10MHZ to 15MHz
LT1116 AI01
Q
5V
CABLE
1N5712
VIN
RS
50
RT
50
LT1116
+
LT1116 AI02
Q
OUTPUT
2k
1k
1k
24pF
5V
10 TO 15MHz
AT CUT
5V
Q
LT1116
+
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