參數(shù)資料
型號: LT1054MJ8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: Switched-Capacitor Voltage Converter with Regulator
中文描述: SWITCHED CAPACITOR REGULATOR, 25 kHz SWITCHING FREQ-MAX, CDIP8
封裝: 0.300 INCH, HERMETIC SEALED, CERDIP-8
文件頁數(shù): 9/26頁
文件大?。?/td> 444K
代理商: LT1054MJ8
SLVS033F FEBRUARY 1990 REVISED NOVEMBER 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Supply voltage V
CC
alternately charges C
IN
to the input voltage when C
IN
is switched in parallel with the input supply
and then transfers charge to C
OUT
when C
IN
is switched in parallel with C
OUT
. Switching occurs at the oscillator
frequency. During the time that C
IN
is charging, the peak supply current is approximately 2.2 times the output current.
During the time that C
IN
is delivering a charge to C
OUT
, the supply current drops to approximately 0.2 times the output
current. An input supply bypass capacitor supplies part of the peak input current drawn by the LT1054 and averages
the current drawn from the supply. A minimum input-supply bypass capacitor of 2
μ
F, preferably tantalum or some
other low equivalent-series-resistance (ESR) type, is recommended. A larger capacitor is desirable in some cases.
An example of this would be when the actual input supply is connected to the LT1054 through long leads or when
the pulse currents drawn by the LT1054 might affect other circuits through supply coupling.
In addition to being the output terminal, V
OUT
is tied to the substrate of the device. Special care must be taken in
LT1054 circuits to avoid making V
OUT
positive with respect to any of the other terminals. For circuits with the output
load connected from V
CC
to V
OUT
or from some external positive supply voltage to V
OUT
, an external transistor must
be added (see Figure 14). This transistor prevents V
OUT
from being pulled above GND during startup. Any small
general-purpose transistor such as a 2N2222 or a 2N2219 device can be used. Resistor R1 should be chosen to
provide enough base drive to the external transistor so that it is saturated under nominal output voltage and maximum
output current conditions.
R1
V
OUT
I
OUT
R1
CIN
Load
VOUT
VREF
OSC
VCC
CAP
GND
CAP+
FB/SD
VIN
VOUT
COUT
Pin numbers shown are for the P package.
+
+
1
2
3
4
LT1054
8
7
6
5
Figure 14. Circuit With Load Connected from V
CC
to V
OUT
(4)
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