參數(shù)資料
型號： LT1028MH
廠商： LINEAR TECHNOLOGY CORP
元件分類： 運動控制電子
英文描述： Hex Noninverting Drivers 14-SOIC 0 to 70
中文描述： OP-AMP, 180 uV OFFSET-MAX, 75 MHz BAND WIDTH, MBCY8
封裝： METAL CAN, TO-5, 8 PIN
文件頁數(shù)： 4/20頁
文件大?。?/td> 439K
代理商： LT1028MH
4
LT1028/LT1128
SYMBOL PARAMETER
V
OS
Input Offset Voltage
V
OS
Average Input Offset Drift
Temp
I
OS
Input Offset Current
I
B
Input Bias Current
Input Voltage Range
CMRR
Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
A
VOL
Large-Signal Voltage Gain
CONDITIONS
(Note 1)
(Note7)
MIN
TYP
15
0.1
MAX
80
0.8
MIN
TYP
30
0.2
MAX
125
1.0
UNITS
G
μ
V
G
μ
V/
°
C
V
CM
= 0V
V
CM
= 0V
G
15
±
30
65
22
±
40
±
12.0
124
132
25.0
18.0
±
12.7
±
10.5
8.2
130
±
240
nA
nA
V
dB
dB
G
±
120
G
±
10.5
±
12.0
110
114
5.0
4.0
±
11.5
±
12.7
±
9.5
±
11.0
±
10.5
106
107
3.0
2.5
±
11.5
±
9.0
V
CM
=
±
10.5V
V
S
=
±
4.5V to
±
18V
R
L
≥
2k, V
O
=
±
10V
R
L
≥
1k, V
O
=
±
10V
R
L
≥
2k
R
L
≥
600
(Note 9)
G
124
132
25.0
18.0
G
G
V/
μ
V
V/
μ
V
V
OUT
Maximum Output Voltage Swing
G
V
V
I
S
Supply Current
G
8.0
10.5
11.5
mA
V
S
=
±
15V, 0
°
C
≤
T
A
≤
70
°
C, unless otherwise noted.
LT1028AC
LT1128AC
LT1028C
LT1128C
ELECTRICAL C
HARA TERISTICS
SYMBOL PARAMETER
V
OS
Input Offset Voltage
V
OS
Average Input Offset Drift
Temp
I
OS
Input Offset Current
I
B
Input Bias Current
Input Voltage Range
CMRR
Common-Mode Rejection Ratio
PSRR
Power Supply Rejection Ratio
A
VOL
Large-Signal Voltage Gain
CONDITIONS
MIN
TYP
20
0.2
MAX
95
0.8
MIN
TYP
35
0.25
MAX
150
1.0
UNITS
G
μ
V
G
μ
V/
°
C
V
CM
= 0V
V
CM
= 0V
G
20
±
35
80
28
±
45
±
11.8
123
131
20.0
14.0
±
12.5
8.7
160
±
280
nA
nA
V
dB
dB
G
±
140
G
±
10.4
±
11.8
108
112
4.0
3.0
±
11.0
±
12.5
±
10.4
102
106
2.5
2.0
±
11.0
V
CM
=
±
10.5V
V
S
=
±
4.5V to
±
18V
R
L
≥
2k, V
O
=
±
10V
R
L
≥
1k, V
O
=
±
10V
R
L
≥
2k
G
123
131
20.0
14.0
G
G
V/
μ
V
V/
μ
V
V
OUT
I
S
Maximum Output Voltage Swing
Supply Current
G
V
G
8.5
11.0
12.5
mA
V
S
=
±
15V, –40
°
C
≤
T
A
≤
85
°
C, unless otherwise noted. (Note 10)
LT1028AC
LT1128AC
LT1028C
LT1128C
ELECTRICAL C
HARA TERISTICS
on an RMS basis) is divided by the sum of the two source resistors to
obtain current noise. Maximum 10Hz current noise can be inferred from
100% testing at 1kHz.
Note 6:
Gain-bandwidth product is not tested. It is guaranteed by design
and by inference from the slew rate measurement.
Note 7:
This parameter is not 100% tested.
Note 8:
The inputs are protected by back-to-back diodes. Current-limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds
±
1.8V, the input current should be limited to 25mA.
Note 9:
This parameter guaranteed by design, fully warmed up at T
A
=
70
°
C. It includes chip temperature increase due to supply and load
currents.
Note 10:
The LT1028/LT1128 are not tested and are not quality-
assurance-sampled at –40
°
C and at 85
°
C. These specifications are
guaranteed by design, correlation and/or inference from –55
°
C, 0
°
C, 25
°
C,
70
°
C and /or 125
°
C tests.
The
G
denotes specifications which apply over the full operating
temperature range.
Note 1:
Input Offset Voltage measurements are performed by automatic
test equipment approximately 0.5 sec. after application of power. In
addition, at T
A
= 25
°
C, offset voltage is measured with the chip heated to
approximately 55
°
C to account for the chip temperature rise when the
device is fully warmed up.
Note 2:
Long Term Input Offset Voltage Stability refers to the average
trend line of Offset Voltage vs. Time over extended periods after the first
30 days of operation. Excluding the initial hour of operation, changes in
V
OS
during the first 30 days are typically 2.5
μ
V.
Note 3:
This parameter is tested on a sample basis only.
Note 4:
10Hz noise voltage density is sample tested on every lot with the
exception of the S8 and S16 packages. Devices 100% tested at 10Hz are
available on request.
Note 5:
Current noise is defined and measured with balanced source
resistors. The resultant voltage noise (after subtracting the resistor noise
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