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參數(shù)資料
型號(hào): LT1022CN8
廠商: Linear Technology
文件頁(yè)數(shù): 6/12頁(yè)
文件大小: 0K
描述: IC PREC OP-AMP JFET HI-SPD 8-DIP
標(biāo)準(zhǔn)包裝: 50
放大器類型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 24 V/µs
增益帶寬積: 8MHz
電流 - 輸入偏壓: 30pA
電壓 - 輸入偏移: 100µV
電流 - 電源: 7mA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): ±10 V ~ 18 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1317 (CN2011-ZH PDF)
3
LT1022
1022fa
ELECTRICAL CHARACTERISTICS
The denotes the specifications which apply over the full operating temperature range of VCM = 0V, 0°C ≤ TA ≤ 70°C. VS = ± 15V,
unless otherwise noted.
LT1022CH
LT1022AC
LT1022CN8
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
H Package
140
480
180
1000
V
(Note 2)
N8 Package
300
1700
V
Average Temperature
H Package
1.3
5.0
1.8
9.0
V/°C
Coefficient of Input Offset Voltage
N8 Package (Note 6)
3.0
15.0
V/°C
IOS
Input Offset Current
Warmed Up, TA = 70°C
15
80
18
100
pA
IB
Input Bias Current
Warmed Up, TA = 70°C
±50
±200
±60
±250
pA
AVOL
Large-Signal Voltage Gain
VO = ±10V, RL = 2k
80
250
60
250
V/mV
CMRR
Common Mode Rejection Ratio
VCM = ±10.4V
85
93
80
91
dB
PSRR
Power Supply Rejection Ratio
VS = ±10V to ±18V
86
103
84
101
dB
VOUT
Output Voltage Swing
RL = 2k
±12
±13.1
±12
±13.1
V
LT1022AM
LT1022M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
(Note 2)
230
750
300
1500
V
Average Temperature
(Note 6)
1.5
5.0
2.0
9.0
V/°C
Coefficient of Input Offset Voltage
IOS
Input Offset Current
Warmed Up, TA = 125°C
0.3
2.0
0.30
3.0
nA
IB
Input Bias Current
Warmed Up, TA = 125°C
± 0.5
± 4.0
± 0.7
± 6.0
nA
AVOL
Large Signal Voltage Gain
VO = ±10V, RL = 2k
40
120
35
120
V/mV
CMRR
Common-Mode Rejection Ratio
VCM = ±10.4V
85
92
80
90
dB
PSRR
Power Supply Rejection Ratio
VS = ±10V to ±17V
86
102
84
100
dB
VOUT
Output Voltage Swing
RL = 2k
±12
±12.9
±12
±12.9
V
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power;
(b) at TA = 25°C, with the chip self-heated to approximately 45°C
to account for chip temperature rise when the device is fully warmed up.
Note 3: 10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
Note 4: This parameter is tested on a sample basis only.
Note 5: Current noise is calculated from the formula: in = (2qIB)1/2, where
q = 1.6 10 –19 coulomb. The noise of source resistors up to 1G swamps
the contribution of current noise.
Note 6: Offset voltage drift with temperature is practically unchanged when
the offset voltage is trimmed to zero with a 100k potentiometer between
the balance terminals and the wiper tied to V +. Devices tested to tighter
drift specifications are available on request.
The denotes the specifications which apply over the full operating temperature range of – 55°C ≤ TA ≤ 125°C. VS = ±15V, VCM = 0V,
unless otherwise noted.
LT1022AM
LT1022M, LT1022CH
LT1022AC
LT1022CN8
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
GBW
Gain-Bandwidth Product
f = 1MHz
8.5
8.0
MHz
IS
Supply Current
5.2
7.0
5.2
7.0
mA
Settling Time
A = +1 or A = –1
10V Step to 0.05%
0.9
s
10V Step to 0.02%
1.3
s
Offset Voltage Adjustment Range
RPOT = 100k
±7
±7mV
VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted.
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