參數(shù)資料
型號： LSI53C1010R
英文描述： LSI53C1010R Ultra160 SCSI controller
中文描述： LSI53C1010R Ultra160的SCSI控制器
文件頁數(shù)： 18/166頁
文件大?。?/td> 1330K
代理商： LSI53C1010R
2-2
General Design Considerations
This section covers some of the key highlights of the 8032 architecture
and some important Archimedes compiler features. The remainder of the
chapter provides an overview of the LSI53C040 firmware and general
design considerations necessary to use this firmware most effectively.
2.1.1 8032 Architecture Features
The architectural features of the 8032 microcontroller are key to the
understanding and use of the LSI53C040 firmware. These features
include:
Section 2.1.1.1, “Register Banks,” page 2-2
,
Section 2.1.1.2,
“Memory Areas,” page 2-2
, and
Section 2.1.1.3, “Special Function
Registers,” page 2-4
.
2.1.1.1 Register Banks
Four register banks that contain eight registers each in the 8032 reside
in the lower 128 bytes of the internal RAM. See
Figure 2.1
for an
example of these register banks.
2.1.1.2 Memory Areas
The 8032 architecture supports a number of physically separate memory
areas for program and data. Each memory area offers certain
advantages and disadvantages. Refer to the
Intel 8-bit Embedded
Controllers
databook or other 8051 reference material for more
information about the 8032 memory architecture. The following sections
briefly discuss program memory, the internal data memory, and the
external data memory.
Program Memory –
Since the 8032 is a ROMless variant of the 8051,
an external 16 Kbytes memory is required to hold the program code. The
LSI53C040 has the ability to automatically download this program code
from a serial EEPROM over the TWS bus into the external
16 Kbytes memory space.
Internal Data Memory –
The 8032 contains 256 bytes of internal data
memory, which can be read and written. The first 128 bytes of internal
data memory are both directly addressable and indirectly addressable.
The upper 128 bytes of data memory (from 0x80 to 0xFF) can be
addressed only indirectly. With indirect addressing, the referenced
register contains the address of the register or cell that actually contains
the data to be used. There is also a 16-byte area starting at 0x20 that is
bit-addressable. See
Figure 2.1
for more detailed information.
相關PDF資料
PDF描述
LSI53C1020 LSI53C1020 PCI-X to Ultra320 SCSI Controller technical manual v2.0 6/02
LSI53C1030 LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller technical manual v2.0 5/02
LSI53C120 LSI53C120 Ultra SCSI Bus Expander technical manual v1.0 8/01
LSI53C140 LSI53C140 Ultra2 SCSI Bus Expander technical manual v2.1 9/01
LSI53C141 LSI53C141 SCSI Bus Expander technical manual v2.1 11/00
相關代理商/技術參數(shù)
參數(shù)描述
LSI53C1020 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C1020 PCI-X to Ultra320 SCSI Controller technical manual v2.0 6/02
LSI53C1020A384BGALEADFREE 制造商:LSI Corporation 功能描述:
LSI53C1030 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller technical manual v2.0 5/02
LSI53C1030-456BGA(C0) 制造商:LSI Corporation 功能描述:
LSI53C1030-E1 制造商:LSI Corporation 功能描述:
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