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參數(shù)資料
| 型號(hào)： | LSI403Z |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | LSI403Z digital signal processor |
| 中文描述： | LSI403Z數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 57K |
| 代理商： | LSI403Z |
LSI403Z Digital Signal Processor
O V E R V I E W
The LSI403Z is a low power 16-bit fixed-point digital signal processor (DSP)
based on the LSI Logic ZSP400 DSP core. The device has been designed for
applications requiring high throughput and flexibility coupled with a high speed
I/O, such as Voice over Networks CPE/IAD devices and audio applications. The
LSI403Z is capable of a maximum clock rate of 150 MHz for 600 MIPS peak
performance and sustained effective throughput of 300 DSP MIPS (MACs). The
device is also software compatible with all other products in the ZSP architecture,
and offers an unrivalled combination of code density, performance and ease of use.
M E M O R Y
The internal memory structure of the LSI403Z comprises of 16K words of
on-chip instruction memory, 16K words of on-chip data memory, 2K words on-
chip boot ROM, and on-chip peripherals. Additionally, the boot ROM provides
start-up and self-test capabilities. Both synchronous and asynchronous devices
are supported including sync-burst SRAM. The external memory is logically
segmented into instruction, data, and peripheral spaces.
D M A
The DMA controller of the LSI403Z supports zero-overhead instruction or data
transfers to or from the entire 32K words of internal RAM to the memory interface
unit, host processor interface, or serial ports. The eight DMA channels are
segmented between four “indexed” and four “non-indexed” channels. Indexed
channels have the ability to multiplex and de-multiplex data. Indexed channels can
also operate in non-indexed mode.
F E AT U R E S
150 MHz operation at 1.8V
2 high-speed serial/TDM ports
(T1/E1 framer, H.100/H.110 bit
stream compatible)
Low power modes
32K words on-chip RAM, 2K
words on-chip ROM
8-channel DMA controller
On-board PLL for clock generation
32-/16-bit external memory interface
2 on-board timers
IEEE 1149.1-compliant JTAG port
for real-time emulation
B E N E F I T S
300 MMAC sustained DSP
performance at 150 MHz
Direct interfacing to standard
telecommunications interfaces,
reducing system cost
High data throughput without
processor overhead
Low power per channel
Flexibility to optimize power
consumption
High data bandwidth to off-chip
devices
RTOS support and increased
system integration
Low overhead on chip debug
Ideal for Voice over DSL IAD designs
The
Communications
Company
TM
MAC 1
MAC 2
ALU 2
ALU 1
Register File
PPL
Boot ROM
Program
Memory
16Kx16
Data
Memory
16Kx16
DMA
MXU
Load/Store Buffer
Xbus
Serial Port 0 Serial Port 1
HPI
PIO
Pipeline
Control
Unit
Data Unit
D-Cache
Instruction Unit
I-Cache
Bus I/F Unit
ICU
DEU
JTAG
DSP Core
64b
32b
64b
32b
64b
64b
32b
Figure 1. LSI403Z Functional Block Diagram
ZSP
TM
ARCHITECTURE PERFORMANCE WITH HIGH-END INTEGRATION
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