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參數(shù)資料
| 型號(hào)： | LS7566 |
| 廠商： | LSI Corporation |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 24-BIT FOUR-AXES QUADRATURE COUNTER |
| 中文描述： | 24位的4軸正交計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | LS7566 |
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A, the B and the INDX inputs. If a logic level at any of
these inputs remains stable for a minimum of two filter
clock periods, it is validated as a correct logic state.
The PCK input is common to all four axes, but the filter
clock frequency for any axis is set by its associated
MDR0 register.
In non-quadrature mode no filter clock is used and the
PCK input should be tied to either VDD or GND.
x0A
(pin 24),
x0B
(Pin 25) Inputs. These are the A and B
count inputs in axis x0. These inputs can configured to
function either in quadrature mode or in non-quadrature
mode. The configuration is made through MDR0. In
quadrature mode, A and B clocks are 90 degrees out of
phase. When A leads B in phase, the CNTR counts up
and when B leads A in phase, the CNTR counts down.
In non-quadrature mode, A is the count input and B is the
count direction control input. When B is
high
, positive
transitions at the A input causes the CNTR to count
up
.
Conversely, when B is
low
, the positive transition at the
A input causes the CNTR to count
down
.
In quadrature mode, A and B inputs are sampled by an
internal filter clock generated from the PCK input. In non-
quadrature mode A and B inputs are not sampled and the
count clocks are applied to the CNTR bypassing the filter
circuit.
x1A
(Pin 27),
x1B
(Pin 28),
x2A
(Pin 32),
x2B
(Pin33),
x3A
(Pin 35),
x3B
(Pin36)
These are the A and B inputs corresponding to axes x1,
x2 and x3. Functionally, they are identical with the A and
B inputs of axis x0.
x0INDX
(Pin 23) Input. The INDX input in axis x0. The
INDX input can be configured by MDR0 to function as
load_CNTR or reset_CNTR or load_OL input. In quad-
rature mode the INDX input is sampled with the same
filter clock used for sampling the A and the B inputs. In
quadrature mode the INDX must satisfy the phase
relationship with A and B in which INDX is at the active
level during a minimum of quarter cycle of both A and B
high or both A and B low. The active level can be
configured to be either high (positive index) or low
(negative index).
In non-quadrature mode the INDX input is not sampled
and can be applied in any phase relationship with respect
to the A and B inputs.
The INDX input can be either enabled or disabled in both
quadrature and non-quadrature modes.
x1INDX
(Pin 26),
x2INDX
(Pin 29),
x3INDX
(Pin 34)
These are the INDX inputs corresponding to axes x1, x2
and x3. Functionally, they are identical with the INDX
input of axis x0.
INT/
(Pin 45)
Output
The INT/ output is the common interrupt output for all the
axes. When any of the ISR bits gets set, INT/ switches
low indicating an asserted interrupt. The axis generating
the interrupt can then be identified by reading the ISR
register.
x0FLGa
(Pin 48) Output. The FLGa output in axis x0. The
FLGa output is configured by MDR1 register to function as
either Carry or Borrow or Compare flag. A Carry flag is
generated when the CNTR overflows, a Borrow flag is
generated when the CNTR underflows and a Compare
flag is generated by the condition, CNTR = PR. The FLGa
can be configured to produce outputs in either latched
mode or instantaneous mode. In the latched mode when
the selected event of Carry or Borrow or Compare has
taken place, the FLGa switches low and remains low until
the status register, STR is cleared. In the instantaneous
mode a negative pulse is generated instantaneously when
the event takes place. The FLGa output can be disabled
to remain at a fixed logic high.
x1FLGa
(Pin 46),
x2FLGa
(Pin 41),
x3FLGa
(Pin 39)
These outputs are the FLGa outputs corresponding to
axes x1, x2 and x3, respectively. Functionally, they are
identical with the FLGa output of axis x0.
x0FLGb
(Pin 47) Output. The FLGb output in axis x0. The
FLGb output is configured by MDR1 to function as either
Index or Sign or Up/Down status indicator.
When configured as Sign, the FLGb output remains high
when CNTR is in an underflow state (caused by down
counts at or below zero), indicating a negative number.
When the CNTR counts up past zero, FLGb switches low,
indicating a positive number.
When configured as Up/Down indicator, a high at the
FLGb indicates that the current count direction is up
(incremental) whereas a low indicates that the direction is
down (decremental).
The FLGb output can be disabled to remain at a fixed
logic high.
x1FLGb
(Pin 42),
x2FLGb
(Pin 40)
x3FLGb
(Pin 38)
These are the FLGb outputs corresponding to axes x1, x2
and x3 respectively. Functionally, they are identical with
the FLGb output of x0.
7566-032205-6
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